GS9091B Datasheet, PDF (56/71 Pages) Gennum Corporation – GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI

A
0
0
Application layer
read pointer
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Internal write
pointer
ANC_DATA
B
Application layer
read pointer
0
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Internal write ⁰
pointer
1023
ANC_DATA_SWITCH = LOW
1023
C
0
Application layer ⁰
read pointer
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
Internal write
pointer
ANC_DATA
%%
1023
ANC_DATA_SWITCH = HIGH
1023
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written
to second half of FIFO starting at adress zero. Application layer continues to
read from the first half of the FIFO.
D
Internal write
pointer
0
%%
Application layer
read pointer
0
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
1023
ANC_DATA_SWITCH = LOW
1023
ANC_DATA_SWITCH toggled LOW. First half of FIFO cleared and ancillary
data read from second half of FIFO. Device continues to write ancillary data
to second half of FIFO.
1023
1023
ANC_DATA_SWITCH = HIGH
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to first half of
FIFO starting at address zero. Application layer continues to read from second half
of FIFO. Toggling ANC_DATA_SWITCH back LOW will clear the second half of the
FIFO and go back the situation depicted in box A.
NOTE: At least 1100 PCLK cycles must pass between toggles of the ANC_DATA_SWITCH bit.
The bit must be toggled at a point where no extraction is occuring (i.e. the ANC signal is LOW).
Figure 3-13: Ancillary Data Extraction and Reading
3.10.4 Bypass Mode
The internal FIFO is in bypass mode when the FIFO_EN or IOPROC_EN pin is set LOW,
or the FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 11b. By
default, the FIFO_MODE[1:0] bits are set to 11b by the device whenever both the
SMPTE_BYPASS and DVB_ASI pins are LOW; however, the FIFO_MODE[1:0] bits may
be programed as required.
In bypass mode, the FIFO is not inserted into the video path and data is presented to the
output of the device synchronously with the PCLK output. The FIFO will be disabled and
placed in static mode to save power.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
38910 - 2
July 2008
56 of 71
Proprietary & Confidential