GS9091B Datasheet, PDF (31/71 Pages) Gennum Corporation – GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI

3.7 DVB-ASI Functionality
DVB_ASI functionality is only supported in Manual mode.
In Manual mode, the DVB_ASI pin must be set to logic HIGH in order to enable DVB-ASI
operation. The SMPTE_BYPASS pin will be ignored.
When using DVB-ASI mode, the use of application circuit in Figure 3-4 on page 31 is
suggested. The use of this application circuit will prevent the internal PLL from false
locking to a DVB-ASI signal harmonic rather than the 270MHz fundamental. This
application circuit will detect the false lock state and restart the on-chip PLL. The
application circuit does this by detecting if the LOCK has been de-asserted for longer
than ~700μs, and if so resets the PLL by discharging the loop filter capacitor through a
CMOS switch.
The applications circuit below show how this can be implemented by using a STG719
switch as a reference. Other low leakage CMOS switches may also be substituted within
the circuit.
In 1
2
3
STG719
6 S2
5D
4 _S1
STG719
6
1
5
RESTART_PLL
OUT
IN
FPGA or
Microcontroller
GPIO
LF+
GS9090B
LF- GS9091B
LOCKED
Figure 3-4: GS9091B False Lock Restart Circuit
The circuit above can be implemented using either a small state machine in an FPGA or
general purpose I/O on a microcontroller in combination with some firmware.
Typically, a system using the GS9091B will have an existing FPGA and/or
microcontroller that may have some spare I/O that can be used to implement the false
lock restart circuit. The choice of method will depend on what spare system resources
are available. In either case, the waveform shown in Figure 3-5 on page 31 represents
how the PLL restart must be driven. The delay values of 700μs and 20μs are nominal but
the values can be longer. In the case where the SDI inputs are not driven with a valid
DVB-ASI signal, the RESTART_PLL signal should be repeated indefinitely as long as
LOCKED remains de-asserted.
DDI
POWER_OK
LOCKED
RESTART_PLL
VALID DVB-ASI INPUT SIGNAL
~700µs
~20µs
VALID DVB-ASI INPUT SIGNAL
~700µs
~20µs
Figure 3-5: GS9091B False Lock Restart Circuit Waveforms of False Lock After
Power-up and False Lock After a Signal Switch.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
38910 - 2
July 2008
31 of 71
Proprietary & Confidential