GS2960A Datasheet, PDF (5/99 Pages) Gennum Corporation – Ancillary data extraction

List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 22
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 22
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength......... 23
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 23
Figure 3-5: VBG .............................................................................................................................................. 23
Figure 3-6: LB_CONT .................................................................................................................................... 24
Figure 3-7: Loop Filter .................................................................................................................................. 24
Figure 3-8: SDI/SDI and TERM .................................................................................................................. 24
Figure 3-9: SDO/SDO .................................................................................................................................... 24
Figure 4-1: Level A Mapping ...................................................................................................................... 25
Figure 4-2: Level B Mapping ...................................................................................................................... 26
Figure 4-3: 27MHz Clock Sources ............................................................................................................ 29
Figure 4-4: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 32
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 33
Figure 4-6: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 34
Figure 4-7: DDR Video Interface - 3G Level A ..................................................................................... 37
Figure 4-8: DDR Video Interface - 3G Level B ...................................................................................... 38
Figure 4-9: Delay Adjustment Ranges .................................................................................................... 39
Figure 4-10: Switch Line Locking on a Non-Standard Switch Line ............................................... 40
Figure 4-11: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 44
Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 44
Figure 4-13: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 45
Figure 4-14: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 45
Figure 4-15: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 45
Figure 4-16: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 45
Figure 4-17: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 45
Figure 4-18: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 47
Figure 4-19: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 47
Figure 4-20: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 48
Figure 4-21: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 48
Figure 4-22: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 49
Figure 4-23: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 50
Figure 4-24: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 50
Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 51
Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 51
Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 52
Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 52
Figure 4-29: 2K Feature Enhancement ................................................................................................... 56
Figure 4-30: Y/1ANC and C/2ANC Signal Timing .............................................................................. 63
Figure 4-31: Ancillary Data Extraction - Step A .................................................................................. 70
Figure 4-32: Ancillary Data Extraction - Step B ................................................................................... 71
Figure 4-33: Ancillary Data Extraction - Step C .................................................................................. 71
Figure 4-34: Ancillary Data Extraction - Step D .................................................................................. 72
Figure 4-35: GSPI Application Interface Connection ........................................................................ 74
Figure 4-36: Command Word Format ..................................................................................................... 75
Figure 4-37: Data Word Format ................................................................................................................ 76
Figure 4-38: Write Mode .............................................................................................................................. 76
Figure 4-39: Read Mode ............................................................................................................................... 76
Figure 4-40: GSPI Time Delay .................................................................................................................... 76
Figure 4-41: In-Circuit JTAG ...................................................................................................................... 92
Figure 4-42: System JTAG ........................................................................................................................... 92
Figure 4-43: Reset Pulse ............................................................................................................................... 93
Figure 7-1: Pb-free Solder Reflow Profile .............................................................................................. 98
GS2960A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54384 - 2
September 2012
5 of 99