GS3140 Datasheet, PDF (25/40 Pages) Semtech Corporation – Multi-Rate Adaptive 3G SDI Equalizer

Table 4-6: GSPI Timing Parameters (Continued)
Parameter
Symbol
Equivalent
SCLK Cycles
Min
Typ
Max
SDO after SCLK falling edge
t₆
1.9
—
7.5
CS high after final SCLK falling edge
t₇
0
—
—
Input data hold time
t₈
1
—
—
CS high time
t₉
46.9
—
—
SDIN to SDOUT combinatorial delay
—
—
5
Max. chips daisy chained at max
SCLK frequency (32 MHz)
When host clocks in SDOUT
—
—
1
Max. frequency for 32
daisy-chained devices
data on rising edge of SCLK
—
—
2.1
Max. chips daisy-chained at max.
SCLK frequency (32 Mhz)
When host clocks in SDOUT
—
—
3
Max. frequency for 32
daisy-chained devices
data on falling edge of SCLK
—
—
2.2
Notes:
1. Parameter is an exact multiple of SCLK periods and scales proportionally
2. t_{cmd_GSPI_conf} inter-command delay must be used whenever modifying HOST_CONF_REG_0 register at address 0x00
Units
ns
ns
ns
ns
ns
GS3140
chips
MHz
GS3140
chips
MHz
4.11.7 Single Read/Write Access
Single read/write access timing for the GSPI interface is shown in Figure 4-8 to
Figure 4-12.
When performing a single read or write access, one Data Word is read from/written to
the device per access. Each access is a minimum of 32-bits long, consisting of a
Command Word and a single Data Word. The read or write cycle begins with a
high-to-low transition of the CS pin. The read or write access is terminated by a
low-to-high transition of the CS pin.
The maximum interface clock rate is 32MHz and the inter-command delay time
indicated in the figures as t_cmd, is a minimum of 3 SCLK clock cycles. After modifying
values in HOST_CONF_REG_0, the inter-command delay time, t_{cmd_GSPI_config}, is a
minimum of 4 SCLK clock cycles.
For read access, the time from the last bit of the Command Word to the start of the data
output, as defined by t₅, corresponds to no less than 4 SCLK clock cycles at 32MHz.
GS3140
Final Data Sheet
PDS-060939
Rev.1
May 2015
www.semtech.com
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