GS2986 Datasheet, PDF (25/41 Pages) Gennum Corporation – Standards indication in Auto mode

reading hard-wired pin configuration, pin override settings and the values of all status
monitoring pins.
There is an optional 3-state feature available in the Control Status Registers (CSR) that
puts the SPI SDO to high-impedance when it’s not being used (Register: TOP_1, bit: 2).
The maximum operating speed of the SPI is 10MHz.
4.15.2 Legacy Mode & Start-up
In legacy mode, basic configuration of the device including a subset of equalizer settings
are available at the pin level. In this mode, register settings are automatically set to
default so that the IC is live at power-up.
4.15.3 Host Interface Mode & Start-up
In host interface mode, the user gains access to Control and Status Registers (CSRs) that
manage advanced features. In this mode, equalizer and de-emphasis settings are set
through the CSR.
The SPI control port is functional at start-up without the need for a separate, external
reset signal. However, all internal registers must be set to their default state by issuing a
required Reset Command via the SPI.
This is done by setting the R bit (reset) LOW in the command word. This will guarantee
the CSR will not start up in a random state.
A simple way to issue the required reset of the CSR is to hold the slave device’s SDI input
LOW for an entire 64 cycle WRITE communication. Details of the WRITE operation are
found in section 4.15.6 below.
4.15.4 Clock & Data Timing
The SPI signals are Serial Data Input (SDI), Serial Data Output (SDO), active-low Chip
Select (CS), and Serial Clock Input (SCK). The host interface operates in SPI Mode 0, i.e.
the SDI input will latch data in on the rising edge of SCK. The SDO data output will
transition on falling edges of SCK. Data is transmitted or received on the SPI port MSB
first LSB last.
SCK
CS
Cycle #
1 2345678
SDI ^{z 1} 2 ^{3 4 5 6 7 8 z}
SDO ^{z 1 2 3 4 5 6 7 8 z}
Figure 4-4: Data Clock Alignment
GS2986 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
52134 - 3
July 2012
25 of 41