GS7025_09 Datasheet, PDF (17/23 Pages) Gennum Corporation – PRO-LINX Serial Digital Receiver

GS7025 may lock at 243MHz being the first 27MHz sideband below 270MHz. In this
case, when normal bit density signals are transmitted, the PLL will correctly lock onto
the proper 270MHz carrier.
3.2.5 Output Data Muting
The GS7025 internally mutes the SDO and SDO outputs when the device is not locked.
When muted, SDO/SDO are latched providing a logic state to the subsequent circuit and
avoiding a condition where noise could be amplified and appear as data.
The output data muting timing is shown in Figure 3-5.
DDI
NO DATA TRANSITIONS
LOCK
SDO
VALID
DATA
OUTPUTS MUTED
VALID
DATA
Figure 3-5: Output Data Muting Timing
3.2.6 Clock Enable
When CLK_EN is HIGH, the GS7025 SCO/SCO outputs are enabled. When CLK_EN is
LOW, the SCO/SCO outputs are placed in a high-impedance state and float to VCC.
Disabling the clock outputs results in a power savings of 10%. It is recommended that the
CLK_EN input be hard wired to the desired state. For applications which do not require
the clock output, connect CLK_EN to Ground and connect the SCO/SCO outputs to VCC.
3.2.7 Stressful Data Patterns
All PLL's are susceptible to stressful data patterns which can introduce bit errors in the
data stream. PLL's are most sensitive to patterns which have long run lengths of 0's or 1's
(low data transition densities for a long period of time). The GS7025 is designed to
operate with low data transition densities such as the SMPTE 259M-C pathological
signal (data transition density = 0.05).
3.3 I/O Description
3.3.1 High Speed Analog Inputs (SDI/SDI)
SDI/SDI are high-impedance inputs which accept differential or single-ended input
drive.
Figure 3-6 shows the recommended interface when a single-ended serial digital signal
is used.
GS7025 PRO-LINX™ Serial Digital Receiver
Data Sheet
13813 - 7
October 2009
17 of 23