GS7025_09 Datasheet, PDF (15/23 Pages) Gennum Corporation – PRO-LINX Serial Digital Receiver

3.2.2 Frequency Acquisition
The core PLL is able to lock if the incoming data rate and the PLL clock frequency are
within the PLL capture range (which is slightly larger than the loop bandwidth). To assist
the PLL to lock, the GS7025 uses a frequency acquisition circuit.
The frequency acquisition circuit sweeps the VCO control voltage so that the VCO
frequency changes from -10% to +10% of the centre frequency. Figure 3-4 shows a
typical sweep waveform.
t_swp
t_sys
V_LF
A
T_cycle
T_cycle = t_swp + t_sys
Figure 3-4: Typical Sweep Waveform
The VCO frequency starts at point A and sweeps up attempting to lock. If lock is not
established during the up sweep, the VCO is then swept down. The probability of
locking within one cycle period is greater than 0.999. If the system does not lock within
one cycle period, it attempts to lock in the subsequent cycle.
The average sweep time, (tswp) is determined by the loop filter component (CLF1) and
the charge pump current (ICP):
t_SWP
=
4----C_{----L---F--1-}
3I_CP
The nominal sweep time is approximately 121μs when CLF1 = 15nF and ICP = 165μA
(RVCO = 365Ω).
An internal system clock determines tsys (see Section 3.2.3 Logic Circuit).
3.2.3 Logic Circuit
The GS7025 is controlled by a finite state logic circuit which is clocked by an
asynchronous system clock. That is, the system clock is completely independent of the
incoming data rate. The system clock runs at low frequencies, relative to the incoming
data rate, and thus reduces interference to the PLL.The period of the system clock is set
by the COSC capacitor and is:
t_sys
=
9.6
×
4
10
×
C_O
S
C^[
second
s
]
The recommended value for tsys is 450μs (COSC = 4.7nF)
GS7025 PRO-LINX™ Serial Digital Receiver
Data Sheet
13813 - 7
October 2009
15 of 23