GS4915 Datasheet, PDF (12/26 Pages) Gennum Corporation – ClockCleaner™

3. Detailed Description
GS4915 Data Sheet
3.1 Functional Overview
The GS4915 provides a low jitter clock output when fed with an HD or SD video
clock input. Other input clock frequencies between 12MHz and 165MHz can be
automatically passed through to the GS4915 outputs.
An internal 2:1 mux allows the user to select between a differential (CML/LVDS
compatible) or single-ended (LVCMOS) input clock. Both a single-ended
LVCMOS-compatible and an LVDS-compatible differential output are provided.
The GS4915 may operate in either auto or fixed frequency mode. In auto mode,
the device will automatically clean the selected input clock if its frequency is found
to be one of the supported SD or HD clock rates. In fixed mode, the user selects
only one of these frequencies to be cleaned.
In addition, the device allows the user to select between auto or manual bypass
operation. In autobypass mode, the GS4915 will automatically bypass its cleaning
stage and pass the input clock signal directly to the output whenever the device is
unlocked which includes the case where the input frequency is something other
than the five frequencies supported. In manual bypass mode, the input signal
passes through directly to the output.
The GS4915 can optionally double the output frequency for 74.25MHz or
74.175MHz HD clocks in order to provide optimal jitter performance of some
serializers.
The GS4915 also provides the user with a 2-state skew control. The output clocks
produced by the device may be advanced by ¼ of an output CLK period in order
to accommodate downstream setup and hold requirements.
The GS4915 is designed to operate with the GO1555 VCO.
The GS4915 Clock Cleaner complements Gennum's GS4911B Clock and Timing
Generator for implementing a video genlock solution. Whereas the GS4911B itself
cleans low-frequency jitter, the GS4915 is designed to clean primarily the higher
frequency jitter of clocks generated by the GS4911B.
3.2 Clock Inputs
The GS4915 contains two separate input buffers to accept either a differential or
single-ended input clock. The applied clock(s) can be any video clock needing
cleaning, although typically it will be the video clock specifically used for
serialization.
The frequency of the applied clock signal(s) must be between 12MHz and 165MHz.
The clock input buffers use a separate power supply of +1.8V DC supplied via the
IN_VDD pin.
39145 - 3 November 2007
12 of 26