GL9701 Datasheet, PDF (58/75 Pages) GENESYS LOGIC – PCI ExpressTM to PCI Bridge

GL9701 PCI Express^TM to PCI Bridge
0
RWS
6
RWS
7
RWS
8
RWS
12
RWS
0 Receiver Error Mask
0 Bad TLP Mask
0 Bad DLLP Mask
0 REPLAY_NUM Rollover Mask
0 Replay Timer Timeout Mask
6.49 Offset 118h: Advanced Error Capabilities and Control Register
Bits Type Default
Description
First Error Pointer – Identifies the bit position of the first error
4:0
ROS
00h
reported in the Uncorrectable Error Status register.
ECRC Generation Capable – This bit indicates that
5
RO
1b
the device is capable of generating ECRC.
ECRC Generation Enable – This bit when set
6
RWS
0b
enables ECRC generation.
ECRC Check Capable – This bit indicates that the
7
RO
1b
device is capable of checking ECRC.
ECRC Check Enable – This bit when set enables
8
RWS
0b
ECRC checking.
6.50 Offset 11ch: Header Log Register
Bits
127:0
Type
ROS
Default
Description
0h Header Log – Header of TLP associated with error
6.51 Offset 12ch: Secondary Uncorrectable Error Status Register
Bits Type Default
Description
0
RW1CS
0 ^{Target-Abort on Split Completion Status}
1
RW1CS
0 ^{Master-Abort on Split Completion Status}
2
RW1CS
0 ^{Received Target-Abort Status}
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