GL9701 Datasheet, PDF (51/75 Pages) GENESYS LOGIC – PCI ExpressTM to PCI Bridge

GL9701 PCI Express^TM to PCI Bridge
Device Control register.
Fatal Error Detected – This bit indicates status of Fatal errors
2
RW1C 0b detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
Unsupported Request Detected – This bit indicates that the
device received an Unsupported Request. Errors are logged in this
3
RW1C
0b
register regardless of whether error reporting is enabled or not in
the Device Control register.
AUX Power Detected – Devices that require AUX power report
4
RO
0b
this bit as set if AUX power is detected by the device.
Transactions Pending – This bit when set indicates that the
device has issued Non-Posted Requests which have not been
5
RO
0b completed. A device reports this bit cleared only when all
outstanding Non-Posted Requests have completed or have been
terminated by the Completion Timeout mechanism.
15:6 RsvdZ 000h ^RsvdZ
6.32 Offset 7ch: PCI Express Link Capabilities Register
Bits
3:0
9:4
11:10
14:12
17:15
23:18
31:24
Type
RO
RO
RO
RO
RO
RsvdP
RO
Default
Description
Maximum Link Speed – This field indicates the maximum Link
0001b speed of the given PCI Express Link. Defined encodings are:
0001b 2.5 Gb/s Link
Maximum Link Width – This field indicates the maximum width
00001b
of the given PCI Express Link.
Active State Power Management (ASPM) Support –
00b
Not supported
L0s Exit Latency – This field indicates the L0s exit latency for the
111b
given PCI Express Link.
L1 Exit Latency – This field indicates the L1 exit latency for the
111b
given PCI Express Link.
00h ^RsvdP
01h ^{Port Number – This field indicates the PCI Express Port}
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