GA50JT12-247_15 Datasheet, PDF (7/12 Pages) GeneSiC Semiconductor, Inc. – OFF Silicon Carbide Junction Transistor

GA50JT12-247
Section V: Driving the GA50JT12-247
Drive Topology
TTL Logic
Constant Current
High Speed – Boost Capacitor
High Speed – Boost Inductor
Proportional
Pulsed Power
Gate Drive Power
Consumption
High
Medium
Medium
Low
Lowest
Medium
Switching
Frequency
Low
Medium
High
High
High
N/A
Application Emphasis
Wide Temperature Range
Wide Temperature Range
Fast Switching
Ultra Fast Switching
Wide Drain Current Range
Pulse Power
Availability
Coming Soon
Coming Soon
Production
Coming Soon
Coming Soon
Coming Soon
A: Static TTL Logic Driving
The GA50JT12-247 may be driven using direct (5 V) TTL logic after current amplification. The (amplified) current level of the supply must meet
or exceed the steady state gate current (I_G,steady) required to operate the GA50JT12-247. The power level of the supply can be estimated from
the target duty cycle of the particular application. I_G,steady is dependent on the anticipated drain current I_D through the SJT and the DC current
gain h_FE, it may be calculated from the following equation. An accurate value of the h_FE may be read from Figure 4.
𝐼𝐼_{𝐺𝐺 ,í µí± í µí± í µí± í µí± í µí± í µí± í µí± í µí± í µí± í µí± í µí± í µí±} 
≈
𝐼𝐼_{𝐷𝐷}
ℎ_{𝐹𝐹𝐹𝐹} (𝑇𝑇,
𝐼𝐼_{𝐷𝐷} )
∗
1.5
5V
TTL
Gate Signal
5/0V
TTL i/p
D
C_G
R_{G G}
I_G,steady
S
Figure 22: TTL Gate Drive Schematic
B: High Speed Driving
The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate
current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 23 which features a positive
current peak during turn-on, a negative current peak during turn-off, and continuous gate current to remain on.
Figure 23: An idealized gate current waveform for fast switching of an SJT.
An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q_G, for turn-on is supplied by a burst of high
gate current, I_G,on, until the gate-source capacitance, C_GS, and gate-drain capacitance, C_GD, are fully charged.
𝑄𝑄_{𝑜𝑜𝑜𝑜} = 𝐼𝐼_{𝐺𝐺,𝑜𝑜𝑜𝑜} ∗ ₁
𝑄𝑄_{𝑜𝑜𝑜𝑜} ≥ 𝑄𝑄_{𝑔𝑔} + 𝑄𝑄_{𝑔𝑔}
Dec 2015
Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
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