MB85R2001_09 Datasheet, PDF (9/16 Pages) Fujitsu Component Limited. – Memory FRAM CMOS 2 M Bit (256 K × 8)

MB85R2001
■ TIMING DIAGRAMS
1. Read Cycle Timing (CE1, CE2 Control)
CE1
tRC
tCA1
tPC
CE2
tCA2
A0 to A17
OE
I/O1 to I/O8
tAS
tAH
Valid
H or L
tES
tRP
tCE1,
tCE2
tLZ
Invalid
tOH
Valid
tOHZ
Invalid
2. Read Cycle Timing (OE Control)
tCA1
CE1
CE2
tCA2
A0 to A17
tAS
tAH
Valid
H or L
tRC
OE
tRP
tPC
I/O1 to I/O8
tOE
tLZ
Invalid
tOH
Valid
tOHZ
Invalid
High-Z
High-Z
DS05-13107-4E
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