MB15U10 Datasheet, PDF (8/19 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz Prescaler

MB15U10
b) Data setting description
• Table 1 : MA0 to MA16 : Divide ratio of the binary 17-bit main counter (PLL1)
Divide Ratio
(MA)
M
A
16
M
A
15
M
A
14
M
A
13
M
A
12
M
A
11
M
A
10
M
A
9
M
A
8
M
A
7
M
A
6
M
A
5
M
A
4
M
A
3
M
A
2
M
A
1
M
A
0
1024
00000010000000000
1025
00000010000000001
•
•••••••••••••••••
Note: • Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071)
• Table 2 : MB0 to MB16 : Divide ratio of the binary 17-bit main counter (PLL2)
Divide Ratio
(MB)
M
B
16
M
B
15
M
B
14
M
B
13
M
B
12
M
B
11
M
B
10
M
B
9
M
B
8
M
B
7
M
B
6
M
B
5
M
B
4
M
B
3
M
B
2
M
B
1
M
B
0
1024
1025
•
00000010000000000
00000010000000001
•••••••••••••••••
Note: • Divide ratios less than 1,024 are prohibited. (Divide ratio = 1,024 to 131,071)
• Table 3 : R0 to R11 : Divide ratio of the binary 12-bit reference counter
Divide Ratio R R R R R R R R R R R R
(R)
11 10 9 8 7 6 5 4 3 2 1 0
6
000000000110
7
000000000111
•
••••••••••••
Note: • Divide ratios less than 6 are prohibited. (Divide ratio = 6 to 4,095)
• Table 4 : Divide ratio select bit of reference frequency (PLL1 and PLL2)
SR
Divide ratio of reference Divide ratio of reference
frequency (PLL1)
frequency (PLL2)
0
R
R
1
R
2R
Note: R = Programmed value with R0 to R11 bits
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