MB15U10 Datasheet, PDF (7/19 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer On-Chip 1.1 GHz Prescaler

MB15U10
s FUNCTIONAL DESCRIPTIONS
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider, program-
mable divider (PLL1) and programmable divider (PLL2) separately by means of address setting.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored
data is latched.
a) Serial data input format
(MSB)
Direction of data input
(LSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
X X X POO C CX X P P P P P X X 0 0 0 1
0 L L RR
SS3 2 1
AB 1 2
12
M M M MMM M MMM M MM M M MM 0 1 0 0
A A A AAA A AAA A AA A A AA
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 TSR R RRR R RR R R RR0 1 0 1
S R 11 10 9 8 7 6 5 4 3 2 1 0
M M M MMM M MMM M MM M M MM 0 1 1 0
B B B BBB B BBB B BB B B BB
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Auxiliary bit for test (no need at ordinary use)
0000
Data setting
MA0 to 16 : Divide ratio setting bits of the main counter (PLL1)
MB0 to 16 : Divide ratio setting bits of the main counter (PLL2)
R0 to 11 : Divide ratio setting bits of the reference counter
SR
: Divide ratio select bit of reference frequency (PLL1 and PLL2)
P0 to 3 : Setting bits of P0 to P3 output pins
OLA, B : Select bits of P0/LD pin output
CR1, 2 : Select bits of charge pump output current
PS1, 2 : Power saving mode control bits
TS
: Test bits (Set ”0” at ordinary use.)
X
: Dummy bits (Set ”0” or ”1”.)
0
: Set ”0”
Note: Start data input with MSB first.
Address
[ See Table 1 ]
[ See Table 2 ]
[ See Table 3 ]
[ See Table 4 ]
[ See Table 5 ]
[ See Table 6 ]
[ See Table 7 ]
[ See Table 8 ]
[ See Table 9 ]
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