MB15F78UL Datasheet, PDF (8/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F78UL
s FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO = [ (P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (16 or 32 for TX-PLL, 32 or 64 for RX-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of TX/RX-
PLL sections, programmable reference dividers of TX/RX-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
CN1
CN2
The programmable
reference counter
for the TX-PLL
0
0
The programmable
reference counter
for the RX-PL
1
0
The programmable
counter and the swallow
counter for the TX-PLL
0
1
The programmable
counter and the swallow
counter for the RX-PLL
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
(LSB)
Data Flow
(MSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X
CS
: Charge pump current select bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2 : LD/fout output setting bit
CN1, 2 : Control bit
X
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
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