MB15F78UL Datasheet, PDF (12/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F78UL
4. Serial data input timing
Divide ratio setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
1st data
2nd data
Control bit Invalid data
Data
MSB
LSB
Clock
t1
t2
t7
LE
t3
t6
t4
t5
Parameter
t1
t2
t3
t4
Min.
20
20
30
30
Typ.




Max.




Unit
ns
ns
ns
ns
Parameter
t5
t6
t7
Min.
100
20
100
Typ.



Max.



Unit
ns
ns
ns
Note : LE should be “L” when the data is transferred into the shift register.
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