MB91220 Datasheet, PDF (69/88 Pages) Fujitsu Component Limited. – 32-bit Microcontroller

MB91220/S Series
[External reset input specifications (INITX) and internal reset signal cancellation timing]
• When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the
internal reset signal to transmit all reset signals to the internal logic (Max 8 µs at 32 MHz) .
• The following chart shows how to set the timing for instruction execution start (start of application operation)
after external reset input.
Time from external reset input to instruction start = Max 256 tcp + 61 tcp
• Timing Chart
INITX
Internal reset
Min
10 tcp
Internal reset input timing
Max 256 tcp
61 tcp
Internal reset cancellation timing
[Pin state in external bus mode]
In the external bus mode, it is not guaranteed to hold the RAM value upon external reset (INITX = “0”) input.
Beside that, the value of the internal bus is to be output to each pin during the time between the internal reset
input and its cancellation.
• Timing Chart (Pin State for External Bus Mode : 1)
INITX
Internal reset
Pin state of
external bus
Min
10 tcp
Max 256 tcp
Hi-Z
Value immediately
before reset
61 tcp
Initial value at reset
69