MB39C308 Datasheet, PDF (51/60 Pages) Fujitsu Component Limited. – 6ch DC/DC Converter IC for LPIA Platform VR

MB39C308
2. External switching FET channel (CH1, CH2)
For the loop consisting of the input capacitor (CIN), high-side FET and low-side FET of each channel, take the
most care of making the current loop as tight as possible.
The input capacitor (CIN), high-side FET and low-side FET, inductor (L) and output capacitor (CO) should be
connected to the surface layer as much as possible using short and thick connections. In addition, avoid making
connections to theses components via the through hole.
Large transient current flows through the connections between the FET gate and OUT1H,OUT1L,OUT2H and
OUT2L pins. Make this lines as short and thick as possible (ex. 0.5 mm width).
PVDD1, PVDD2, LX1, LX2 pins sense the voltage between drain and source at high-side FET. Connect the
PVDD1 or PVDD2 pin to the drain pin of high-side FET directly. Avoid connecting to the other part on the line.
Connect the LX1 or LX2 pin to the source pin of high-side FET directly. Connect the bootstrap capacitor as in
the following graph and avoid connecting to the other part on the line. Furthermore, large transient current also
flows through the connection to the LX pin. Make the line as short and thick as possible (exp: PVDD1, PVDD2,
LX1, LX2 lines are 0.5 mm width).
When not connecting the PVDD and the LX pins to the drain or the source pin of the high-side FET as the layout
below, an error may occur in PWM/PFM switch current value and the OCP setting value because of the error
occurred in the current sense value.
• Example layout
MB39C308
CB1, CB2 pin
PVDD1, PVDD2 pin
LX1, LX2 pin
Connect the PVDD pin to
the drain pin of high-side
FET directly so as to sense
the drain voltage at high-
side FET. The line shouldn't
be connected to the other
parts.
Drain pad
VIN
High-side FET
Bootstrap
capacitor
Through hole
CIN
PGND
Loop
CO
L
VO
Source pad
Low-side FET
Connect the LX pin to
the source pin of high-
side FET directly so as to
sense the source voltage
at high-side FET.
The line shouldn't be
connected to the other
parts except the boot-
strap capacitor.
To FB1,FB2 pin
DS04-27261-6E
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