MB40C338V Datasheet, PDF (5/19 Pages) Fujitsu Component Limited. – 3 ch 8-bit 162 MSPS A/D Converter

s BLOCK DIAGRAM
VESD
AVDD DVDD
MB40C338V
RVRT RVRTM VRB VRBM RVM GVM BVM
PCLP
RADIN
RVIN
RVCLP
× 1.9
OF
AMP + CLAMP + A/D
× 3 ch
A ch
8
8
8 bit A/D
Buffer
RDA0
∼ RDA7
B ch
8
8
8 bit A/D
Buffer
RDB0
∼ RDB7
HSYNC
POL
(1 bit)
PLL block
2 bit (0 ∼ 3 CLK)
CLK Delay
Delay
6 bit
(32 divide, 2CLK)
RESET _1/2
PD
CP
VCO
MUX
DIV
2 bit
(1 ∼ 1/8)
Buffer
Buffer
Buffer
Buffer
Buffer
Buffer
ADCLKA
ADCLKB
AVSS
DVSS
DSYNC
DSYNCB
CLK
CLKB
HHOLD
Counter
(12 bit)
11 bit Shift Reg
COUT
LPF EXPCLKB EXCLK
EXPCLK
Filter
PVSS PVDD CK DATA CS
5