MB40C338V Datasheet, PDF (12/19 Pages) Fujitsu Component Limited. – 3 ch 8-bit 162 MSPS A/D Converter

MB40C338V
s TIMING DIAGRAM
• Straight Output Mode (Timing Diagram 1)
VIHD
HSYNC input
VILD
VOHD
CLK output
CLKB output
VOLD
VOHD
DSYNC output
VOLD
VOHD
ADCLKA output
VOLD
VOHD
ADCLKB output
VOLD
ADIN input
tpd (HSYNC-CLK)
tpd (CLK-DSYNC)
tpd (CLK-ADCLK1)
N
N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
tAD
VOHD
DA0 to DA7 output
VOLD
VOHD
DB0 to DB7 output
VOLD
tpd (CLK-DATA1)
X
X
X
X
X
X
X
X
N N+1 N+2 N+3
ALL “L” fix
VOHD
OF output
VOLD
X
X
X
X
X
X
X
X
N N+1 N+2 N+3
• ADIN input - Sampling at CLK rising (at CLKB falling)
• DA0 to DA7 - Output (after 5 CLK + tpd (CLK-DATA1) from sampling ) at CLK rising (at CLKB falling)
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