MB85RC256VPNF-G Datasheet, PDF (4/36 Pages) Fujitsu Component Limited. – 256 K (32 K × 8) Bit I2C

MB85RC256V
■ I²C COMMUNICATION PROTOCOL
The I²C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
data transfer can only be initiated by the master, which will also provide the serial clock for synchronization.
The SDA signal should change while SCL is the “L” level. However, as an exception, when starting and
stopping communication sequence, SDA is allowed to change while SCL is the “H” level.
• Start Condition
To start read or write operations by the I²C bus, change the SDA input from the “H” level to the “L” level while
the SCL input is in the “H” level.
• Stop Condition
To stop the I²C bus communication, change the SDA input from the “L” level to the “H” level while the SCL
input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the
standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and
enters the standby state.
• Start Condition, Stop Condition
SCL
SDA
H or L
Start
Stop
Note : At the write operation, the FRAM device does not need the programming wait time (tWC) after issuing the
Stop Condition.
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DS501-00017-3v0-E