MB3827 Datasheet, PDF (30/41 Pages) Fujitsu Component Limited. – 6-ch DC/DC Converter IC With Synchronous Rectification for voltage step-up and step-down

MB3827
s METHOD OF SETTING TIME CONSTANT FOR TIMER-LATCH SHORT PROTECTION
CIRCUIT
The short detection comparator (SCP comparator) in each of the channels constantly compares the error
amplifier output level to the reference voltage and the −IN(C)8 terminal (pin 23).
While the switching regulator load conditions are stable on all channels, or when the voltage level at the −IN(C)8
pin is higher than the reference voltage, LOG_SCP output remains at “H” level, transistor Q1 is on, and the
CSCP terminal (pin 31) is held at input standby voltage (VSTB =: 50mV).
If the load conditions change rapidly due to a short-circuiting of load, causing the output voltage to drop, or if
the voltage at the −IN(C)8 terminal falls below the reference voltage level, the output from the short detection
comparator on the corresponding channel or the input at the −IN(C)8 terminal goes to “H” level. This causes
transistor Q1 to turn off and the external short protection capacitor CSCP connected to the CSCP pin to charge
at 1.0 µA.
Short Detection Time (tPE)
tPE(sec) =: 0.68 × CSCP (µF)
When the capacitor CSCP is charged to the threshold voltage VTH =: 0.68 V the SR latch is set, and the external
PNP is turned off (dead time is set to 100%). At this point the SR latch input is closed and the CSCP terminal
is held at input latch voltage (VI =: 50 mV).
Protection timer-latch short protection circuit
External PNP transistor
A
R1
44
−IN1
R2
1.0 V
SCP
− Comp.1
+
Drive
1−1
Drive
1−2
52
OUT1−1
50
OUT1−2
23
−IN (C) 8
1.26 V
SCP
− Comp.8
+
LOG_SCP
CSCP
31
1 µA
CSCP
Q1
bias
S
R
Timer-latch short
protection circuit
UVLO
Drive
7
bias
1
OUT7
Ref
Power
ON/OFF CTL
27
CTL1−4, 7
30