MB86434 Datasheet, PDF (3/38 Pages) Fujitsu Component Limited. – 5V Single Power Supply Audio Interface Unit (AIU)

MB86434
s PIN DESCRIPTION
Pin No. Symbol I/O A/D
Description
1 CAG
G A Analog ground pin for codec block. To be set to 0 V.
2 VRH
O A Bypass capacitor connector pin for the A/D D/A reference voltage generator
circuit. Place capacitor between VRH and CAG pins.
3 SGC
O A Bypass capacitor connector pin for the signal ground potential generator
circuit. Place capacitor between SGC and CAG pins.
4 VDDAC P A Analog power supply pin for codec block. To be set within range 4.75 to
5.25 V.
5 N.C.
— — Not connected. To be left open.
6 N.C.
— — Not connected. To be left open.
7 SYNC
I D PCM codec send/receive synchronization signal input pin. Operating clock
frequencies 8 kHz. CMOS interface. Other frequencies may cause codec
block to power-down.
8 CLK
I D Send/receive PCM signal series bit rate setting input pin. Data rate for µ-law,
A-law modes may be set to any level in the range 64 k to 3.152 MHz, and for
linear in the range 256 k to 3.152 MHz. Constant H or L level signal will
cause part of codec block to power-down. CMOS interface.
9 DIN
I D PCM signal input pin. This signal is picked up internally at the fall of the CLK
signal. CMOS interface.
10 DOUT
O D PCM signal output pin. Data is output in sync with the rise of the CLK signal.
After data output, loses PLL synchronization, and at power-down this signal
is fixed at H level. CMOS interface.
11 VDD
P D Digital power supply pin. To be set within range 4.75 to 5.25 V.
12 DG
G D Digital ground pin. To be set to 0V.
13 PSC0
14 PSC1
15 PSC2
I D Power-down control signal input pin.
CMOS interface. Used with PSC1,2
pins for power-down settings.
PSC 2 1 0
I D Power-down control signal input pin.
CMOS interface. Used with PSC0,2
pins for power-down settings.
0 0 0 Full power-down
1 0 0 VREF operating
— 1 0 Tone operating
— — 1 All operations available
I D Power-down control signal input pin. (—: value not determined)
CMOS interface. Used with PSC0,1
pins for power-down settings.
16 SRD
I D 9-bit serial data input pin. CMOS interface. Data is written at the rise of the
signal from this pin.
17 SRC
I D Clock input pin for 9-bit serial data writing. CMOS interface. Data is written
at the rise of this pin.
18 STB
I D Serial data latch strobe signal. Data is latched by the L level signal. CMOS
interface. On-chip pull-down resistance.
19 XPRST
I D Digital reset signal input pin. CMOS interface. L level: internal latch
initialization H level: normal operation
(Continued)
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