MB86434 Datasheet, PDF (24/38 Pages) Fujitsu Component Limited. – 5V Single Power Supply Audio Interface Unit (AIU)

MB86434
5. Power Saving Modes
(1) Mode Selection
The MB86434 power saving modes can be controlled by using the external control signal lines (3 lines). It is also
possible to apply power saving modes to the speaker amps with high power consumption levels by writing changes
to register settings. Whenever the MB86434 changes directly from a power-down mode to normal operating mode,
there is a possibility that speaker tones may be produced. The recommended sequence of coding changes to go
into normal mode is (VREF mode) → (Tone mode) → (Normal mode).
Power Saving Modes
External Ad- Ad-
pins dress dress
Address
0110
Output pin status
Mode
PS PSPS
D
C2 C1C0 D4 D0
SW8
DDD
SW7 SW9 SW6 SW6 SW7 SW9 SW8
All
Power- 0 0 0 — — —
down
VREF 1 0 0 — — —
—1 0 1 1 —
—1 0 0 1 0
Tone — _{1 0 0 1 1}
—1 0 0 1 1
—1 0 0 1 1
—— 1 0 0 0
—— 1 0 0 1
Normal — — 1 0 0 1
—— 1 0 0 1
—— 1 0 0 0
— — — ZA H-Z ZB H-Z H H-Z ZC H-Z H-Z H-Z *
— — — ZA H-Z ZB H-Z H
— — — ZA H-Z ZB H-Z H
1 1 1 ZA H-Z ZB
H
0 1 1 ZA
ZB H-Z H
1 0 1 ZA H-Z H-Z H
1 10
H-Z ZB H-Z H
1 1 1 ZA H-Z ZB
0 1 1 ZA
ZB H-Z
1 0 1 ZA H-Z H-Z
1 10
H-Z ZB H-Z
0 00
ZC H-Z H-Z H-Z *
H-Z H-Z H-Z
H-Z H-Z H-Z
H-Z H-Z H-Z
H-Z H-Z H-Z
H-Z H-Z H-Z
Operating circuit status
Power
supply
current
(mA)
(typ)
SW6 SW7 SW9 SW8
0.0005
0.48
1.8
2.4
4.5
6.8
6.8
8.2
10.3
12.6
12.6
20.9
Note: • : Operational, ×: Power-down, H-Z: High impedance, H: H-level fixed
* : High impedance may not be applied, depending on status of SW6, SW7, SW8.
ZA : EAR and XEAR are floating, however high resistance connection between EAR and XEAR.
ZB : TONE and XTONE are floating, however, high resistance connection between TONE and XTONE, and
between SGO and XTONE.
ZC : Floating, however high resistance connection between OP2 and BTO. Codec in [Normal] mode
operates with SYNC = 8 kHz, CLK = 2048 kHz.
• When RAUD is operating, address 0111 data bit D1 value should be “0” (SW12 off).
• In tone mode, address 0111 data bit D3 should be "0" (SW2 on), and address 0111 data bit D4 should be
“0” (SW14 off).
• When the SYNC and CLK pin signals are fixed at either L-level or H-level, part of the codec unit will go into
power-down mode. At this time the PTBO signal will be SGC level, BTPO will be H-Z, and VRH output will
be approximately 4.0 V.
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