MB15F73UV Datasheet, PDF (3/25 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F73UV
s PIN DESCRIPTION
Pin no.
BCC
Pin
name
I/O
Descriptions
1
GND  Ground pin for OSC input buffer and the shift register circuit.
2
finIF
I
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
3
XfinIF
I
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
4
GNDIF  Ground pin for the IF-PLL section.
5
VCCIF

Power supply voltage input pin for the IF-PLL section, the shift register and the oscil-
lator input buffer.
6
DoIF O Charge pump output for the IF-PLL section.
Power saving mode control pin for the IF-PLL section. This pin must be set at “L”
7
PSIF I when the power supply is started up. (Open is prohibited.)
PSIF = “H” ; Normal mode/PSIF = “L” ; Power saving mode
Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The
8
LD/fout O output signal is selected by LDS bit in a serial data.
LDS bit = “H” ; outputs fout signal/LDS bit = “L” ; outputs LD signal
Power saving mode control for the RF-PLL section. This pin must be set at “L” when
9
PSRF I the power supply is started up. (Open is prohibited. )
PSRF = “H” ; Normal mode/PSRF = “L” ; Power saving mode
10
DoRF O Charge pump output for the RF-PLL section.
11
VCCRF  Power supply voltage input pin for the RF-PLL section.
12 GNDRF  Ground pin for the RF-PLL section
13
XfinRF
I
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
14
finRF
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
15
LE
I When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.
Serial data input pin (with the schmitt trigger circuit)
16
Data I Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
17
Clock
I
Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.
18
OSCIN
I
The programmable reference divider input pin. TCXO should be connected with an
AC coupling capacitor.
3