MBM29F033C Datasheet, PDF (22/46 Pages) Fujitsu Component Limited. – 32M (4M X 8) BIT

MBM29F033C-70/-90/-12
RESET
Hardware Reset
The MBM29F033C device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL)
for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to
the read mode 20 ms after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tristated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires tRH ns of wake up time until outputs are valid for read access.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s
microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The MBM29F033C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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