MB88111 Datasheet, PDF (17/26 Pages) Fujitsu Component Limited. – A/D Converter (With 24-Channel Input at 10-bit Resolution)

MB88111
4. AC Characteristics
(AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C)
Parameter
Symbol
Conditions
Values
Unit
Min. Max.
CCLK clock cycle time
fCLK
fCLK = 1/fCLK
800
1200
KHz
Low-level CCLK clock pulse width
tCKL
—
400
—
ns
High-level CCLK clock pulse width
tCKH
—
400
—
ns
CCLK clock rise time
CCLK clock fall time
tCr
—
–
10
ns
tCf
SCK clock cycle time
fSCK
tSCK = 1/fSCK
400
1200
KHz
Low-level SCK clock pulse width
tSKL
—
400
—
ns
High-level SCK clock pulse width
tSKH
—
400
—
ns
SCK clock rise time
SCK clock fall time
tSr
—
–
10
ns
tSf
SIN setup time
tSIS
—
50
—
ns
SIN hold time
tSIH
—
250
—
ns
Command interval
tCOM
CCLK = 1 MHz
4
—
µs
ENDC reset time
tENR
See “Load conditions.”
–
1
µs
RSTX pulse width
tRSH
—
100
—
ns
RSTX ↑ → SCK ↓ time
tRSS
—
1
—
µs
SCK ↑ → CS1 ↓ time
SCK ↑ → CS2X ↑ time
tCSS
—
500
—
ns
CS1 ↑ → SCK ↓ time
CS2X ↓ → SCK ↓ time
tCSH
—
500
—
ns
SOT output delay time (mode A)
tSODA
See “Load conditions.”
—
300
ns
SOT output delay time (mode B)
tSODB
See “Load conditions.”
—
300
ns
ENDC ↑ → SOT output (mode B)
tSOHB
See “Load conditions.”
—
200
ns
STC command A/D conversion time
tSTC
CCLK = 1 MHz
—
50
µs
ATC command A/D conversion time
tSATC
CCLK = 1 MHz
—
50
µs
ATGX setup time
tSATS
CCLK = 1 MHz
4
—
µs
ATGX hold time
tSATH
CCLK = 1 MHz
2
—
µs
Port input evaluation time
tPOT
CCLK = 1 MHz
—
10
µs
Port input setup time
tPTS
—
0
—
ns
Port input hold time
tPTH
—
0
—
ns
Extended serial HL propagation delay
tSHL
See “Load conditions.”
—
100
ns
Extended serial LH propagation delay
tSLH
See “Load conditions.”
—
100
ns
Noise filter width
tINF
—
15
—
ns
17