MB84VA2006 Datasheet, PDF (12/29 Pages) Fujitsu Component Limited. – 8M (x 8/x 16) FLASH MEMORY & 1M (x 8) STATIC RAM

MB84VA2006-10/MB84VA2007-10
s AC CHARACTERISTICS
• CE Timing
Parameter
Symbols
JEDEC Standard
Description
—
tCCR CE Recover Time
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
CE1s
tCCR
CE2s
Test Setup
-10
Unit
—
Min.
0
ns
tCCR
tCCR
• Read Only Operations Characteristics (Flash)
Parameter
Symbols
JEDEC Standard
Description
tAVAV
tRC Read Cycle Time
tAVQV
tACC Address to Output Delay
tELQV
tCEf Chip Enable to Output Delay
tGLQV
tOE Output Enable to Output Delay
tEHQZ
tDF Chip Enable to Output High-Z
tGHQZ
tDF Output Enable to Output High-Z
tAXQX
tOH
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
—
tREADY RESET Pin Low to Read Mode
—
tELFL
tELFH
CE or BYTE Switching Low or High
Note: Test Conditions–Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
12
Test
Setup
—
CEf = VIL
OE = VIL
OE = VIL
—
—
—
—
—
—
-10
(Note)
Unit
Min. Max.
100
—
ns
—
100 ns
—
100 ns
—
40
ns
—
30
ns
—
30
ns
0
—
ns
—
20
µs
—
5
ns