MB15F08SL Datasheet, PDF (12/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F08SL
s SERIAL DATA INPUT TIMING
1st data
Data
MSB
2nd data
Control bit Invalid data
LSB
Clock
LE
t1
t2
t3
t7
t6
t4
t5
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
t1
t2
t3
t4
Min.
20
20
30
30
Typ. Max.
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
Parameter
t5
t6
t7
Min.
100
20
100
Typ. Max.
–
–
–
–
–
–
Unit
ns
ns
ns
Note: LE should be “L” when the data is transferred into the shift register.
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