MB3873 Datasheet, PDF (11/22 Pages) Fujitsu Component Limited. – Multi-Resonance AC/DC Converter IC

MB3873
s FUNCTIONAL DESCRIPTION
1. Switching Regulator Function
(1) Reference voltage circuit (Ref)
The reference voltage circuit takes the voltage from the Vcc terminal (pin 11) and generates a temperature-
compensated reference voltage ( =: 8V), which is used as the reference voltage supply for the IC internal circuit
bias and detection comparator.
A reference voltage can be output from the VREF terminal (pin 10) at levels up to 10mA.
(2) Triangular-wave oscillator circuit (OSC)
This circuit is used to generate a triangular oscillator waveform, by connecting timing capacitor and resistor to
the CT terminal (pin 2) and RT terminal (pin 1) respectively. The triangular waveform frequency fosc1 is set
according to the timing capacitor and resistor.
The triangular oscillator waveform is input to the IC’s internal dead time timing circuit (One-Shot-DTC), and can
be output from the CT terminal.
(3) Oscillator frequency control circuit (OSC Control)
The oscillator control circuit detects the AC/DC converter output voltage and outputs the PFM control signal to
the triangular wave oscillator. The FB terminal (pin 5) carries the AC/DC converter output voltage at the V/I
converted OSC control current. When an overload occurs, the detection signal to the overload detection circuit
(OCP Comp.) is also output here.
(4) Dead time timing circuit (One-Shot-DTC)
The dead time timing circuit converts the triangular waveform generated by the triangular wave oscillator to a
rectangular wave having a pulse width ( = dead time tDEAD) set by the dead time setup resistor that is connected
to the RD terminal (pin 3).
(5) Output circuit (Drive)
The output circuit has totem pole configuration, and outputs the PFM signal from the OUT terminal (pin 8). The
output circuit power is supplied from the Vcc (O) terminal (pin 9).
2. Protective Function
(1) Undervoltage lockout circuit (UVLO)
Power-on surges and momentary drops in power supply voltage can cause errors in control IC operation, which
can destroy or damage systems. To prevent the error operation, the UVLO Comp.1 circuit detects low voltage
conditions in the supply voltage (Vcc), and sets the VREF terminal (pin 10) to “L” level. The UVLO Comp.2 circuit
detects low voltage conditions in the reference voltage, and sets the OUT pin (pin 8) to “L” level.
Overvoltage/overload/over temperature conditions cause the error detection latch (Latch) to be set. If the VREF
terminal (pin 10) is set to “L” level, and the supply voltage falls below the UVLO circuit threshold voltage (VTHL),
the UVLO Comp.1 resets the error detection latch. Operation is restored when the power supply voltage returns
above the threshold voltage (VTHL) of the UVLO circuit.
The threshold voltage can be set to any desired level by connecting resistor between the ENB terminal (pin 12)
and GND terminal (pin 7), or between the ENB terminal (pin 12) and Vcc terminal (pin 11) (for internal resistance
constants see “BLOCK DIAGRAM”).
(2) Overvoltage detection comparator 1 (OVP Comp. 1)
When the input voltage at the OVP terminal (pin 14) is greater than the threshold voltage (=: 2.5V), the overvoltage
comparator 1 sets the error detection latch, and sets the VREF terminal (pin 10) and OUT terminal (pin 8) to “L”
level.
Note that if OVP Comp.1 is not used, the OVP terminal (pin 14) should be shorted to GND by the shortest path
(see “PROCESSING WHEN OVP PIN IS NOT USED”).
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