MB4053 Datasheet, PDF (10/17 Pages) Fujitsu Component Limited. – 6-Channel 8-BIT A/D Converter

MB4053
s OPERATION DESCRIPTION
Refer to BLOCK DIAGRAM, and DIAGRAM. Address inputs A0 to A2 are used to select the analog input to be
converted, (one of the six analog inputs I1 to I6). The RAMP START input is switched from a logic 1 to a logic
zero. This causes the external ramp capacitor CH to charge at a fixed rate. (Note 1) until it reaches the sum of
the selected analog input voltage and a constant offset voltage VBE1. The RAMP STOP output (open-collector
switches from a logic 0 to logic 1 when the voltage on CH reaches the comparator reference voltage VBE2. The
RAMP START input is switched back to a logic 1 after CH is completely charged. This disconnects the analog
input from CH and allows it to be gin discharging at a fixed rate (Note 2). When the voltage on CH reaches the
comparator reference voltage VBE2 the RAMP STOP output switches back to a logic 0. This completes a
conversion cycle for 1 channel.
The time between the RAMP START input switching (0→1) and RAMP STOP output switching (1→0) is the
RAMP TIME tR. This would be directly proportional to the analog input voltage for the ideal situation where there
was no comparator switching level error, leakage, switching delay times or effect of the impedance of the internal
reference current source. tR can be calculated for the ideal case as follows:
tR = VIN × ^CH
IR
Where: VIN = Analog input voltage to be measured
CH = External ramp capacitor
IR =
VCC - VREF
RREF
This ramp time is converted to a digital representation by counting tR with the microprocessor. If a small error
can be tolerated, the A/D conversion software can be reduced and the conversion time minimized by omitting
corrections.
Notes:
∗_{1 Charge slope =} IA – IR
CH
≥ ^{150 µA – IR}
CH
Where: IA is the acquisition current whose value is determined from the circuit constant in the IC.
∗_{2 Discharge slope = –} IR
CH
10