MB15F03L Datasheet, PDF (10/24 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F03L
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
5
6
•
2047
NNNNNNNNNNN
11 10 9 8 7 6 5 4 3 2 1
00000000101
00000000110
•
•
•
•
•
•
•
•
•
•
•
11111111111
Note: • Divide ratio less than 5 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
ratio
(A)
0
1
•
127
AAAAAAA
7654321
0000000
0000001
•
•
•
•
•
•
•
1111111
Note: • Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
Prescaler
divide ratio
IF-PLL
RF-PLL
SW = ”H”
16/17
64/65
SW = ”L”
32/33
128/129
Table. 7 Phase Comparator Phase Switching Data Setting
fr > fp
fr = fp
fr < fp
VCO polarity
FCIF,RF = H
DoIF,RF
H
Z
L
(1)
FCIF,RF = L
DoIF,RF
L
Z
H
(2)
Note: • Z = High–impedance
• Depending upon the VCO and LPF polarity,
FC bit should be set.
VCO Output
Frequency
(1)
(2)
VCO Input Voltage
LDS
H
L
Table. 8 LD/fout Output Select Data Setting
LD/fout output signal
fout (frIF/RF, fpIF/RF) signals
LD signal
10