FA7622CP Datasheet, PDF (6/8 Pages) Fuji Electric – Bipolar IC For Switching Power Supply Control

4. Timer and latch circuit for overload protection
Figure 9 shows the timer and latch circuit for overload
protection and Fig. 10 shows its timing during an overload.
If the power supply output decreases due to an overload, the
error amplifier output decreases. If the voltage decreases to
less than 0.3V, the switch that clamps the CP pin voltage to
the ground disconnects. This charges capacitor Cp from the
REF pin through the resistor Rcp and the CP pin voltage
increases. When the voltage reaches 1.25V, OUT1 (OUT2)
voltage is clamped to ground.
The N-channel MOSFET (or NPN transistor) connected to the
OUT1 (or OUT2) is turned OFF and cuts off the power supply.
The time tL from when the circuit is overloaded until the power
supply is cut off can be determined as follows:
tL (mS) = 0.67CP (µF) • RCP (kΩ) _{.................(9)}
R CP
FB1
(FB2)
REF
20
Ï©
Ϫ
0.3V
CP
S1
Ï©
CP
Ϫ
1.25V
Fig. 9
5. Overcurrent limiting circuit
This is a pulse-by-pulse overcurrent limiting circuit which
detects and limits the peak of each drain current pulse from the
main switching transistor (MOSFET).
Figure 11 shows the overcurrent limiting circuit and Fig. 12
shows its timing.
This circuit detects a drain current with a voltage sampling
resistor Rs. If a voltage lower than the VCC1 pin voltage by
210mV or more is input to OCL1 (OCL2), the OUT1 (OUT2) is
clamped to ground. At the same time, DT1 (DT2) is raised to
the reference voltage VREF. (This reduces the duty-cycle to
0%)
This circuit has hysteresis to prevent noise from causing
malfunction.
The RS voltage which is propotional to drain current is limited
to 210mV (typ.) and released at 170mV (typ).
FB1(FB2)
DT1(DT2) _CT
CP
PWM output
Voltage waveforms
Fig. 10
DT1
REF (DT2) VCC1
Ϫ
Ï©
VCC1
-0.21V
FA7622CP(E)
OUT1
(OUT2)
1.25V
(Threshold voltage
of CP pin)
Time
OCL1
(OCL2)
Rs
ID
OUT1
(OUT2)
OCL1
(OCL2)
(Similar to ID)
OUT1
(OUT2)
Fig. 11
Voltage waveforms
Fig. 12
VCC1
VCC1
-0.2V
Time
6