FA5640 Datasheet, PDF (33/35 Pages) Fuji Electric – Fuji Switching Power Supply Control IC

FA5640/41/42
(9) Other advice on designing
(1) Surge that occurs at startup due to the minimum
switching frequency limiting
Our lineup includes the one that the minimum switching
frequency and the maximum ON width are set with this IC
to reduce audible noise at the time of starting /stopping.
However, due to this minimum switching frequency function,
there is a period in which the IC is operated in continuous
conduction mode at startup, which may result in increased
surge voltage of the diode on the secondary side. Please
consider using the one that this minimum switching
frequency limiting function was not integrated if the serge of
the diode is a problem.
(2) Switching frequency at the time of bottom skip
This IC detects ON/OFF width using the ZCD pin, thus
controlling the number of times of bottom skips. Bottom skip
is performed up to the point where the IC is turned on at the
fourth bottom depending on the load. At this time,
depending on the specifications of the power supply or
design conditions of the transformer, the switching
frequency at the time of bottom skip may be decreased to
40 kHz or lower. If this frequency interferes with other
devices, causing problems, for example, adjust the
resonance capacitor connected between the drain and the
source of the MOSFET. If the capacitance is reduced, the
resonance frequency increases, allowing the switching
frequency at bottom skip to increase.
(4) Loss calculation
To use the IC within its rating, it is necessary to confirm the
loss of the IC. However, since it is difficult to measure the
loss directly, the method of confirming the loss by
calculation is shown below. If the voltage applied to the VH
pin is defined as VVH, the current fed to the VH pin during
operation as IVHrun, power supply voltage as VCC, supply
current as Iccop1, gate input charge of the MOSFET to be
used as Qg, and switching frequency as fsw, the total loss
Pd of the IC can be calculated using the following formula.
A rough value can be found using the above formula, but
note that Pd is slightly larger than the actual loss value.
Also note that each specific characteristic value has
temperature characteristics or variation.
Example:
If the VH pin is connected to a half-wave rectification
waveform with AC 100 V input, the average voltage to be
applied to the VH pin is approximately 45 V. In this state,
assume that VCC = 15 V, Qg = 80 nC, and fsw = 60 kHz
(when Tj = 25C). Since IVHrun = 30 A and Iccop1 =
0.85mA from the specifications, the standard IC loss can be
calculated as follows:
Pd ≈ 15V x (0.85mA + 80nC x 60kHz) + 45V x 30µA ≈
86.1mW
(3) Preventing malfunction due to negative voltage of the
pin
If large negative voltage is applied to each pin of the IC, the
parasitic devices within the IC may be operated, thus
causing malfunction. Confirm that the voltage of -0.3 V or
less is not applied to each pin.
The vibration of the voltage generated after the MOSFET is
turned-off may be applied to the OUT pin through the
parasitic capacitance, resulting in a case in which negative
voltage is applied to the OUT pin.
In addition, negative voltage may be applied to the IS pin
due to the vibration of surge current generated at the
turn-on of the MOSFET.
In such cases, connect a Schottky diode between each pin
and the GND. The forward voltage of the Schottky diode
can suppress the negative voltage at each pin. In this case,
use a Schottky diode whose forward voltage is low. Figure
33 is a typical connection diagram where a Schottky diode
is connected to the OUT pin.
4
GND
OUT Rg
5
SBD
Fig.33 Negative charge prevention circuit
Fuji Electric Co., Ltd.
AN-064E Rev.1.1
April 2011
33
http://www.fujielectric.co.jp/products/semiconductor/