FA7711V Datasheet, PDF (23/25 Pages) Fuji Electric – FUJI Power Supply Control IC

FA7711V
（11）Protection from negative voltage apply
If rather large negative voltage is applied to any
pins of this IC, internal parasitic elements start
operating, and they may cause malfunctions.
Accordingly, the negative voltage, which is applied to
each Pin of the ICs, must be kept above -0.3V.
In the case of the OUT* pin, in particular, the
oscillation of voltage occurring after MOSFET’s
turning off can be applied to the OUT* pin through
MOSFET’s parasitic capacitance. As a result, there is
a possibility that the negative voltage is applied to the
OUT* pin. If this negative voltage reaches -0.3V or
below, connect an Schottky barrier diode between
OUT* pin and GND as shown in Fig. 21. The
Schottky barrier diode’s forward direction voltage
clamps the voltage applied to the OUT* pin. In this
case, use the Schottky barrier diode with low voltage
drop in forward direction. Other pins should be kept
above -0.3 V also based on the same reasons.
（12）An error pulse at start up
At start up, if rise time of VCC and PVCC pin is too
short, an error pulse, which is several tens µs of
width, may appear on the OUT pin.
The Internal circuit of IC is not stable before VREF
pin voltage rises to about 1V. Therefore, It may
cause an error pulses that a voltage is applied to
PVCC pin before VREG pin voltage raises enough at
start up.
The error pulse may appear when Vcc rise time
from 0V to 12V is less than about a few hundred µs.
In such a case, check the influence of the error
pulse such as blowout of a fuse.
On the other hand, if rise time of Vcc is not so short,
the error pulse will not appear.
12V
Vcc
In the case of an inverting circuit, the negative
voltage charged on the output capacitor will be
applied to VREF pin just after turning off the input
voltage.
If input voltage is turned on during applying a
negative voltage to VREF pin, the negative voltage
may lead malfunction.
This problem is likely to occur in the case of short
interruption.
In such a case, re-start the converter after the output
capacitor is discharged enough or connect a schottky
barrier diode with low forward voltage between VREF
pin and GND as shown in Fig.20.
VIN
VCC
18
PVCC
17
OUT
9
GND
10
PGND
SBD
Fig.19
SBD
4 VREF
IN+
OUT
IN-
9 10
Negative
voltge
Fig.20
about a few hundredμsec
about 1V
VREF
OUT(Nch drive)
Fig.21
（13）Design of phase compensation
A switching power supply supervises output voltage
with error amplifier, constitutes a closed loop, and is
stabilizing voltage by negative feedback.
Phase delay with a smoothing filter and Gain with
the main switching device, etc. is contained in the
negative feedback circuit, and those sum totals
become the phase and the gain in a closed loop.
The phase and the gain have the frequency
characteristic. In a negative feedback circuit, if the
gain remains 0dB or more at the frequency of 180
degrees delayed phase, a circuit will be oscillated.
In order to prevent oscillation, it is necessary to
adjust the phase and the gain of error amplifier.
(Fig.22) Since especially the switching power supply
has repeated ON and OFF at high speed, the minute
high frequency element is contained in the output,
and if you setup the frequency characteristic of the
error amplifier beyond necessity, it has a possibility of
unstable operate and oscillate.
The gain when the phase turns 180 degrees calls
gain margin, the phase when the gain becomes 0dB
calls phase margin. Above 10dB of gain margin and
above 50 degrees of phase margin are desirable
generally and set to this condition in phase
compensation. (Fig.22)
However, gain margin and phase margin against
transient response (sudden change of load, etc.) are
participate as trade-off, therefore when gain margin
and phase margin is larger, transient response
becomes margin-less condition, furthermore over
shoot and under shoot of converter voltage is larger.
Fuji Electric Systems Co., Ltd.
AN-060E Rev.1.0
Jun-2010
23
http://www.fujielectric.co.jp/fdt/scd/