FA7711V Datasheet, PDF (15/25 Pages) Fuji Electric – FUJI Power Supply Control IC

FA7711V
8. Description of each circuit
（1）Reference voltage circuit
The circuit generates the reference voltage (VREF)
of 3.70V±1% compensated in temperature from VCC
voltage. This voltages start to output when the
undervoltage lockout protection (UVLO) is cancelled,
and they stabilize after the supply voltage (VCC)
reaches up to approx. 4.0V or higher.
The voltage (VREF) outputs externally from REF Pin,
therefore, it can serve as a stabilized power source
for reference voltage of Error Amplifier and maximum
output duty setting or the like. The output current
circuit should be within 1mA. (In case of V_CC=8V to
28V should be within 7mA) The V_REF voltage also is
used as a regulated power supply for IC’s internal
blocks.
VREF pin have to connect capacitors C_REF for in
order to stabilize voltages (To determine capacitance,
refer to recommended operating conditions).
（2）Oscillator
The oscillator generates triangular waveforms by
charging and discharging the built-in capacitor.
Any desired oscillation frequency can be obtained
by setting the value of the resistor connected to
RT Pin (Fig. 1).
The voltage oscillates between approximately
1.3V and 2.3V in charging and discharging with
almost the same gradients (Fig. 2). Your desired
oscillation frequency can be determined by
changing the gradient using the resistor (RT)
connected to RT Pin. (Large RT: Low frequency,
small RT: High frequency) The waveforms of
oscillator cannot be observed from the outside
because a Pin for this purpose is not provided.
Approximately DC 1V is output to RT Pin.
The oscillator output is connected to PWM
comparator.
OSC
2
RT
Fig.1
RT
2.3V
RT value:small RT Value:lage
1.3V
Fig.2
Vout1
Vout2
Vout3
VREF
4
IN1+
6
IN1-
7
FB1
8
IN2+
21
IN2-
20
FB2
19
IN3+
24
IN3-
23
FB3
22
Er.AMP1
Er.AMP2
Er.AMP3
For PWM
comparator
For PWM
comparator
For PWM
comparator
Fig.3
（4）PWM comparator
The PWM output generates from the oscillator
output, the error amplifier output (FB1, FB2 and
FB3) and CS voltage (CS1, CS2 and CS3) (Fig. 4).
The oscillator output is compared with the preferred
lower voltage between FB and CS for ch1 and ch3.
While the preferred voltage is lower than oscillator
output, the PWM output is low. While the preferred
voltage is higher than oscillator output, the PWM
output is high. Since the phase of Ch2 is the
opposite phase of ch1 and ch3, higher voltage
between FB2 and CS2 is preferred and while the
preferred voltage is lower than the oscillator output,
the PWM output 2 is high. (Cannot be observed
externally)
The output duty changes sharply around the
minimum and the maximum output duty. This
phenomenon occurs more conspicuously when
operating in a high frequency (i.e. when the
pulse width is narrow). Cautious care must be
taken when using high frequency.
The output polarity of OUT1, OUT2 changes
according to the condition of SEL pin. (See Fig. 6)
OSC
FB1
PW M
Comp.1
CS1
PW M
output.1
Pch
driv e
12 OUT1
（3）Error amplifier
Error Amplifier has the inverting input IN*(-) Pin
(Pin7, Pin20 and pin23) and non-inverted input
IN*(+) Pin (Pin6, Pin21 and pin24) outputting
externally, various circuit can be designed by
kinds of external circuit structures. FB Pins (Pin,
Pin19 and pin22) are the outputs of Error
Amplifiers. Voltage Gain and phase compensation
can be set by connecting a capacitor (C) and a
resistor (R) between FB Pin and IN*(-) Pin.(Fig.
3) For more information about the connection for
each output voltage of power supply, refer to
Design Advice.
PW M
FB2
Comp.2
CS2
PW M
FB3
Comp.3
CS3
PW M
output.2
N/P ch
driv e
PW M
output.3
N/P ch
driv
UVLO
Fig.4
13 OUT2
5 SEL2
15 OUT3
3 SEL3
Fuji Electric Systems Co., Ltd.
AN-060E Rev.1.0
15
Jun-2010
http://www.fujielectric.co.jp/fdt/scd/