FA5546 Datasheet, PDF (20/27 Pages) Fuji Electric – Switching Power Supply Control IC

FA5546/47
(7) Soft start
The LAT terminal is equipped with a soft start function.
Fig.16 shows the LAT terminal voltage at soft start.
The LAT terminal voltage increases to 2.1V at the time of
startup, and then discharged by the constant current
source (70uA typ) down to 1.25V. During this period when
the LAT terminal voltage decreases from 2.1V to 1.5V, soft
start operation is performed.
By adjusting the capacity of the capacitor to be connected
to the LAT terminal, the soft start time can be set.
Approximate soft start time can be calculated using the
following expression:
Fig. 17 Overheat protection function using a
thermistor
Tss = (2.1  1.5)  CLAT/70A = 0.0086  CLAT[F]
Tss[ms] = 8.6  CLAT[F]
where, Tss is soft start time.
The maximum recommended value (2.2uF) of the LAT
terminal capacity CLAT listed in 6-(2) assumes that the
power supply startup time is approximately 20ms. If longer
soft start time is set, the value can be increased to
approximately 10F.
The soft start time is affected by a thermistor connected to
the LAT terminal for overheat protection, if any.
Even if soft start is not necessary, connect a capacitor to
prevent the LAT terminal voltage from decreasing
instantaneously down to 1.05V or lower due to constant
current discharge for soft start, thus causing latch shutdown
to occur.
(See 8-(8) Latch shutdown circuit by an external signal.)
Fig. 16 LAT terminal soft start operation
(8) Latch shutdown circuit by an external signal
The LAT terminal is equipped with a latch shutdown
function. (See Fig.17)
By decreasing the LAT terminal voltage to 1.05V or lower,
the IC enters the latch mode.
To reset the latch mode, interrupt the input voltage, thus
decreasing the VCC voltage to the OFF threshold voltage
(9.8V typ) or lower.
If the external latch shutdown function by the LAT terminal
is not to be used, connect a capacitor only.
Connect an NTC thermistor to the LAT terminal to use the
overheat protective function. (See Fig.17)
Fuji Electric Co., Ltd.
AN-027E Rev.0.4
April -2011
(9) Overvoltage protection circuit (VCC
terminal)
The IC integrates an overvoltage protection circuit for
monitoring the VCC terminal voltage. (See Fig.18)
If the VCC voltage increases and exceeds 26V typ, which is
the reference voltage of the comparator (OVP), the
comparator output is reversed to High level, setting the
latch circuit to perform latch shutdown.
At this time, the startup circuit is subjected to ON/OFF
control to maintain the latch mode, thus keeping the VCC
voltage within the 12V or 13V (typ) range.
To reset the latch mode, interrupt the input voltage to
decrease the VCC voltage down to the OFF threshold
voltage (9.8V typ) or lower.
Since 65s (typ) delay time has been set to the set input of
the latch circuit, the latch mode is not entered even if the
VCC terminal exceeds the detection voltage temporarily.
VCC
6
VH
8 ^{Start up}
VCC
Circut
ON
UVLO
Start up
Management
Logic
Monitor Ctrl
ON
5V
DBL
OUT
5
LAT
LAT
1
OVP
Latch
Set
Latch
Reset
UVLO
Fig. 18 Overvoltage protection circuit
(10) Undervoltage lockout circuit (VCC
terminal)
The IC integrates an undervoltage lockout (UVLO) function
to prevent circuit malfunction that might occur when power
supply voltage decreases. When the VCC voltage
increases from 0V and reaches 18V (typ), the circuit starts
operating. When the VCC decreases down to 9.8V (typ),
the circuit stops operating.
In a state in which the undervoltage lockout function is
actuated to stop IC operation, the OUT terminal is forcibly
made to enter the Low state. The latch mode of the
protection circuit is also reset.
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