FA7703 Datasheet, PDF (17/21 Pages) Fuji Electric – FUJI Power Supply Control IC

FA7703/04
FA7703/7704
(4)Setting the maximum output duty
If you need to control the maximum output duty
in the DC-DC converter circuit, you can control
pulse width by connecting REG terminal to DT
terminal divided with resistors R5 and R6, as
described in Fig. 9. The output duty of the
voltage of DT terminal in this case changes
according to the operation frequency, as
described in the chart of “DT terminal voltage vs.
output duty cycle” characteristic curves. Set the
output duty accordingly based on your required
operation frequency. If the maximum output duty
setting is not needed, be sure to connect DT
terminal directly to REG terminal. In this case,
the pulse width widens up to the output duty of
100%.
The voltage of DT terminal should be set in the
range of 0.65V to 1.1V(typ.). There is a
possibility of distortion of the output pulses if
strong noises or the like are applied to DT
terminal. When conducting pattern wiring, do it
as close to each terminal of the IC as possible.
Besides, it is strongly recommended to connect
a capacitor CDT for a filter of noise prevention.
R5
R6
16 REG
DT1 or DT2
3 15
CDT
GND
7
setting
m axim um
Duty cycle
Fig.9
16 REG
DT1 or DT2
3 15
GND
7
Not needed
maximum Duty
cycle
(5)Pull-up/Pull-down resistor at the output
section
The power source of FA7703/04 to control the
output section is supplied from the voltage of
VREG, the voltage of this power source is
accordingly not stationary below the UVLO
voltage. On the other hand, OUT terminal
becomes unsteady condition while Power supply
voltage is below UVLO voltage. Be sure to
connect a pull-up resistor/pull-down resistor
according to Fig. 10. (See Fig. 10)
(6)Restriction of external discrete
components/Recommended
operating
conditions
To achieve a stable operation of FA7703/04, the
values of external discrete components
connected to VCC, REF, and CS terminals of
this IC should be within the range of
recommended operating conditions. And also the
voltage and the current applied to each terminal
should be within the recommended operating
conditions.
A Pch MOSFET is installed between VCC
terminal and OUT1 terminal, and between VCC
terminal and OUT2 terminal. Since the Pch
MOSFET has a parasitic diode, if the voltage of
OUT1 and OUT2 terminals becomes higher than
the VCC terminal voltage, the current flows from
each terminal to VCC terminal. Cautious care
must be taken accordingly when designing.
VIN
9
Vcc
OUT1
10
GND
7
VIN
9
Vcc
OUT2
8
GND
7
Fig.10
Fuji Electric Systems Co., Ltd.
AN-057E Rev.1.0
Jun-2010
17
http://www.fujielectric.co.jp/fdt/scd/