MB91301 Datasheet, PDF (126/135 Pages) Fuji Electric – 32-Bit Proprietary Microcontroller

MB91301 Series
(Continued)
Pin no.
Port
name
Specified
function
name
Function
name
Bus width
16 bit
81
PG0
INT0/ICU0
PG0
82
PG1
INT1/ICU1
83
PG2
INT2/ICU2
84
PG3
INT3/ICU3
85
PG4
INT4/ATG/
FRCK
86
PG5
INT5/SIN2
87
PG6
INT6/SOT2
88
PG7
INT7/SCK2
90
PJ0
SIN0
91
PJ1
SOT0
92
PJ2
SCK0
93
PJ3
SIN1
94
PJ4
SOT1
95
PJ5
SCK1
96
PJ6
PPG0
97
PJ7
TRG0
98
PH0
TIN0
99
PH1
TIN1/PPG3
100
PH2
TIN2/TRG3
103
PB0
DREQ0
104
PB1
DACK0
105
PB2
DEOP0
106
PB3
DREQ1
107
PB4 DACK1/TRG1
108
PB5 DEOP1/PPG1
109
PB6
IOWR
110
PB7
IORD
122
PA0
CS0
123
PA1
CS1
124
PA2
CS2
125
PA3
CS3
126
PA4
CS4/TRG2
127
PA5
CS5/PPG2
128
PA6
CS6
129
PA7
CS7
132 to 139 P00 to P07 D00 to D07
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PH0
PH1
PH2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
P00 to P07
142 to 144 P10 to P12 D08 to D10 P10 to P12
At initialization (INIT)
Function
name
Bus width
8 bit
Initial
value
PG0
Output Hi-Z
Input ready
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PH0
PH1
PH2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
P00 to P07
P10 to P12
Output Hi-Z
Input ready
Output Hi-Z
Input ready
Output Hi-Z
Input ready
Output Hi-Z
Input ready
H output
Output Hi-Z
Input ready
Sleep
mode
Stop mode
HIZ = 0 HIZ = 1
P : Previous
state held
F : Normal
operation
P : Previous
state held
F : Input
ready
P : Output
Hi-Z
F : Input
ready
Bus released
(BGRNT)
CS
CS not
shared shared
Normal
Normal
operation operation
P : Previous
state held
F : Normal
operation
P : Previous
state held
F : Input
ready
P : Output
Hi-Z
F : Input
ready
Normal
operation
Normal
operation
P : Previous
state held
F : Normal
operation
Previous
state held
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
P : Previous
state held
F : Normal
operation
Previous
state held
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
P : Previous
state held Previous
F : Normal state held
operation
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
H output
H output
Output Hi-Z
F : SREN =
0:H
output,
SREN =
1 : Out-
put Hi-Z
F : SREN =
0:H
output,
SREN =
1 : Out-
put Hi-Z
P : Previous
state held
F : Output
held or
Hi-Z
P : Previous
state held
F : Output
held or
Hi-Z
Output
Hi-Z/input 0
fixed
Output Hi-Z
Output Hi-Z
P : General-purpose port selected, F : Specified function selected
Notes : • The bus width is determined after a mode vector fetch.
• The bus width at initialization time is 8 bits.
126