FA13842 Datasheet, PDF (10/15 Pages) Fuji Electric – CMOS IC(For Switching Power Supply Control)

FA13842, 13843, 13844, 13845
3. Latched shutdown
A typical circuit for latched shutdown is shown in Fig. 8.
The voltage of the OUT terminal is kept low if the voltage of the
COMP terminal is low. The voltage of the COMP terminal
must be set at 0.7V or less in the application temperature
range. (See characteristic curve on page 46 ”COMP to ISNS
offset voltage vs temperature”.)
The source current from the COMP terminal is less than about
1.3mA.
Use of a thyristor such as that shown in Fig. 9 is not effective
because the saturation voltage of the thyristor is higher than
0.7V. When a thyristor is used, increase the voltage of the FB
terminal to more than 3V as shown in Fig.10. In the case of a
latched shutdown, it is necessary to supply a current larger
than the hold current of the thyristor structure circuit or of the
thyristor. This current should be provided through a start-up
resistor from the AC input.
Latched shutdown with a thyristor using the COMP
terminal is not effective.
DB
~+
AC INPUT
~
R1
T1
+
C1
MOSFET
D1
+
C2
7
8
30V
REF
4
2
R4
Latching signal Tr2
D4
1
Tr1
R3
+
ER AMP
Fig. 8
OSC
2R
1R
5
7
8
30V
REF
4
2
Latching signal
1
SCR1
+
ER AMP
Fig. 9
OSC
2R
1R
5
7
8
30V
REF
Latching signal
4
SCR2
2
R5
1
C5
+
ER AMP
OSC
2R
1R
5
Fig. 10
10