UMFT221XE Datasheet, PDF (5/18 Pages) Future Technology Devices International Ltd. – UMFT221XE USB to 8-bit SPI/FT1248 Development Module

UMFT221XE
Version 1.0
Document Reference No.: FT_000651 Clearance No.: FTDI# 293
4.2 Signal Descriptions
Pin No. Name
Type
Description
J1-1,
J2-5
GND
PWR
Module Ground Supply Pins
J1-2
3V3OUT
Power
Input/
Output
3.3V output from integrated L.D.O. regulator. This pin is decoupled with a 100nF
capacitor to ground on the PCB module. The prime purpose of this pin is to provide
the 3.3V supply that can be used internally. For power supply configuration details
see section 5.
J1-3
VCCIO
Power
Input
+1.8V to +3.3V supply to the UART Interface and CBUS I/O pins. For power supply
configuration details see section 5.
J1-4
IO6
I/O
FT1248 Bi-Directional data bit 6.
J1-5
IO5
I/O
FT1248 Bi-Directional data bit 5.
J1-6
IO4
I/O
FT1248 Bi-Directional data bit 4.
J1-7
IO3
I/O
FT1248 Bi-Directional data bit 3.
J1-8
IO2
I/O
FT1248 Bi-Directional data bit 2.
J1-9
IO1
I/O
FT1248 Bi-Directional data bit 1.
J1-10 IO0
I/O
FT1248 Bi-Directional data bit 0.
J2-1
SLD
GND
USB Cable Shield. Connected to GND via a 0 ohm resistor.
J2-2
VBUS
Power
Output
5V Power output from the USB bus. For a low power USB bus powered design, up to
100mA can be sourced from the 5V supply and applied to the USB bus. A maximum
of 500mA can be sourced from the USB bus in a high power USB bus powered design.
Currents up to 1A can be sourced from a dedicated charger and applied to the USB
bus.
J2-3
VCC
Power
Input
5V power input for FT221X. For power supply configuration details see section 5.
J2-4
IO7
I/O
FT1248 Bi-Directional data bit 7.
J2-6
RESET# Input
FT221X active low reset line. Configured with an on board pull-up and recommended
filter capacitor.
J2-7
CBUS3
I/O
Configurable CBUS I/O Pin. Function of this pin is configured in the device internal
MTP ROM. See CBUS Signal Options, Table 4.2.
J2-8
MISO
Output
Master In Serial Out. Used to provide status information to the FT1248 interface
master.
J2-9
SS#
Input FT1248 Chip select input to enable the device interface. Active low logic.
J2-10 SCLK
Input FT1248 Clock input from FT1248 interface master
Table 4.1 – Module Pin Out Description
5
Copyright © 2012 Future Technology Devices International Limited