FT260 Datasheet, PDF (37/58 Pages) Future Technology Devices International Ltd. – Future Technology Devices International Ltd.

FT260 HID-CLASS USB TO UART/I2C BRIDGE IC
Version 1.0
D oc ument N o.: FT _001272 C learance N o.: FT D I#484
7.5 Configuration for System Pins
Figure 7.5 Recommended FT260 Configuration of System Pins
The pins, DCNF0 and DCNF1, will determine one of 3 configurations for the FT260 as defined in Section
5.1. These 2 pins have internal pull-down resistors; these 2 pins can be left floating for logic-0. If logic-1
is applied for DCNF0 and/or DCNF1, a 10K Ohm resistor should be connected to VCCIO as shown in
Figure7.5.
The pin RESETN is the external reset source for the FT260. There is also a power-on-reset (POR) design
in the FT260. If there is no requirement for an external reset, RESETN can be left floating or weakly tied
to logic-high. If an external reset is required in the design, the related circuit in Figure 7.5 can be used
for reference.
The DEBUGGER pin is reserved for debugging purposes and should be tied to VCCIO, the I/O power
domain for the FT260. The pin, STEST_RESETN, is also a reserved pin and should be tied to logic-high.
Note that the GND pin located at pin-29 in Figure 7.5 is the paddle in the bottom side of the QFN28
package. It should be tied together with the GND for FT260.
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