FT2232H Datasheet, PDF (30/60 Pages) Future Technology Devices International Ltd. – DUAL HIGH SPEED USB TO MULTIPURPOSE UART

Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.05
Clearance No.: FTDI#77
4.7.1 MCU Host Bus Emulation Mode Signal Timing – Write Cycle
Figure 4.8 MCU Host Bus Emulation Mode Signal Waveforms – write cycle
NAME
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Description
High address byte is placed on the bus if the extended write is used
Low address byte is put out.
1 clock period for address is set up.
ALE goes high to enable latch. This will extend to 2 clocks wide if IORDY is low.
ALE goes low to latch address and CS# is set active low.
Data driven onto the bus.
1 clock period for data setup.
WR# is driven active low. This will extend to 6 clocks wide if IORDY is low.
WR# is driven inactive high.
CS# is driven inactive, 1/2 a clock period after WR# goes inactive
Data is held until this point, and may now change
Table 4.4 MCU Host Bus Emulation Mode Signal Timings – write cycle
The IORDY “WAIT” states in the read and write cycles assume that the “divide-by-5” has been set in the
clock generation. (This can be set by sending the hex value $8A)
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