FT801 Datasheet, PDF (24/57 Pages) Future Technology Devices International Ltd. – The FT801 is an easy to use graphic controller targeted for embedded applications to generate high-quality Human Machine Interfaces (HMIs). It has the following features

Table 4-9 ROM font Extended ASCII characters
Document No.: FT_000986
FT801 Embedded Video Engine
Datasheet Version 1.0
Clearance No.: FTDI#376
128 Ç 144 É 160 á 176 _░ 192 └ 208 ð 224 Ó 240 -
129 ü 145 æ 161 í 177 _▒ 193 _┴ 209 Ð 225 ß 241 ±
130 é 146 Æ 162 ó 178 _▓ 194 _┬ 210 Ê 226 Ô 242 ‗
131 â 147 ô 163 ú 179 │ 195 _├ 211 Ë 227 Ò 243 ¾
132 ä 148 ö 164 ñ 180 _┤ 196 ─ 212 È 228 õ 244 ¶
133 à 149 ò 165 Ñ 181 Á 197 _┼ 213 ı 229 Õ 245 §
134 å 150 û 166 ª 182 Â 198 ã 214 Í 230 µ 246 ÷
135 ç 151 ù 167 º 183 À 199 Ã 215 Î 231 þ 247 ¸
136 ê 152 ÿ 168 ¿ 184 © 200 _╚ 216 Ï 232 Þ 248 °
137 ë 153 Ö 169 ® 185 _╣ 201 _╔ 217 ┘ 233 Ú 249 ¨
138 è 154 Ü 170 ¬ 186 _║ 202 _╩ 218 ┌ 234 Û 250 ·
139 ï 155 ø 171 ½ 187 _╗ 203 _╦ 219 _█ 235 Ù 251 ¹
140 î 156 £ 172 ¼ 188 _╝ 204 _╠ 220 _▄ 236 ý 252 ³
141 ì 157 Ø 173 ¡ 189 ¢ 205 _═ 221 ¦ 237 Ý 253 ²
142 Ä 158 × 174 « 190 ¥ 206 _╬ 222 Ì 238 ¯ 254 _■
143 Å 159 ƒ 175 » 191 ┐ 207 ¤ 223 _▀ 239 ´ 255 nbsp
Note: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters.
Note: All fonts included in the FT801 ROM are widely available to the market-place for general usage, see
section nine for specific copyright data and links to the corresponding license agreements.
4.4 Parallel RGB Interface
The RGB parallel interface consists of 23 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 signals
each for R, G and B.
Several registers configure the LCD operation of these signals as follow:
REG_PCLK is the PCLK divisor the default is 0, and disables the PCLK output.
PCLK frequency = System Clock frequency / REG_PCLK
PCLK_POL define the clock polarity, =0 for positive active clock edge, and 1 for negative clock
edge.
REG_CSPREAD controls the transition of RGB signals with respect to PCLK active clock edge.
When REG_CSPREAD=0, R[7:2],G[7:2] and B[7:2] signals change following the active edge of
PCLK. When REG_CSPREAD=1, R[7:2] changes a PCLK clock early and B[7:2] a PCLK clock
later, which helps reduce the switching noise.
REG_DITHER enables colour dither; the default is enabled. This option improves the half-tone
appearance on displays. Internally, the graphics engine computes the colour values at an 8 bit
precision; however, the LCD colour at a lower precision is sufficient. The FT801 output is only 6
bits per colour in 6:6:6 formats and a 2X2 dither matrix allow the truncated bits to contribute
to the final colour values.
REG_OUTBITS gives the bit width of each colour channel, the default is 6, 6, 6 bits for each
RGB colour. A lower value means fewer bits are output for each channel allowing dithering on
lower precision LCD displays.
REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route
different LCD panel arrangements. Bit 0 of the register causes the order of bits in each colour
channel to be reversed. Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels
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