FT801 Datasheet, PDF (17/57 Pages) Future Technology Devices International Ltd. – The FT801 is an easy to use graphic controller targeted for embedded applications to generate high-quality Human Machine Interfaces (HMIs). It has the following features

Table 4-3 Host command transaction (SPI)
7
6
5
4
3
2
0
1
Command [5:0]
0
0
0
0
0
0
0
0
0
0
0
0
Document No.: FT_000986
FT801 Embedded Video Engine
Datasheet Version 1.0
Clearance No.: FTDI#376
1
0
0
0
0
0
For I²C command transaction, bytes are packed in the I²C protocol as follows:
[start] <DEVICE ADDRESS + write bit>
<01b,Command[5:0]>
<00h>
<00h> [stop]
Table 4-4 Host Command Table
1st Byte
2nd byte
3rd byte
Command
Description
Power Modes
00000000b 00000000b 00000000b
00h
ACTIVE
Switch from Standby/Sleep modes to
active mode. Dummy read from address
0 generates ACTIVE command.
01000001b 00000000b
01000010b 00000000b
01010000b 00000000b
Clock Switching
01000100b 00000000b
01001000b 00000000b
01100010b 00000000b
01100001b 00000000b
Miscellaneous
01101000b 00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
41h
STANDBY
42h
SLEEP
50h
PWRDOWN
Put FT801 core to standby mode. Clock
gate off, PLL and Oscillator remain on
(default).
Put FT801 core to sleep mode. Clock
gate off, PLL and Oscillator off.
Switch off 1.2V internal regulator. Clock,
PLL and Oscillator off.
44h
CLKEXT
48h
CLKINT
62h
CLK48M
61h
CLK36M
Select PLL input from Crystal oscillator
or external input clock.
Select PLL input from Internal relaxation
oscillator (default).
Switch PLL output clock to 48MHz
(default).
Switch PLL output clock to 36MHz.
68h
CORERST
Send reset pulse to FT801 core. All
registers and state machines will be
reset.
NOTE: Any command code not specified is reserved and should not be used by the software
4.1.7 Interrupts
The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tri-state
(pulled to high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when
any of the interrupt flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK.
Writing a ‘1’ in any bit of REG_INT_MASK will enable the correspond interrupt. Each bit in
REG_INT_FLAGS is set by a corresponding interrupt source. REG_INT_FLAGS is readable by
the host at any time, and clears when read.
Copyright © 2014 Future Technology Devices International Limited
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