FT4222HQ-C-R Datasheet, PDF (20/49 Pages) Future Technology Devices International Ltd. – USB2.0 to QuadSPI/I2C Bridge IC

FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC
1.3
Document No.: FT_001011 Clearance No.: FTDI#405
5.3 I²C Bus Interface
I²C (Inter Integrated Circuit) is a multi-master serial bus invented by Philips. I²C uses two bi-directional
open-drain wires called serial data (SDA) and serial clock (SCL). Common I²C bus speeds are standard
mode (SM) with bit rate up to 100 Kbit/s, fast mode (FM) with bit rate up to 400 Kbit/s, Fast mode plus
(FM+) with bit rate up to 1 Mbit/s, and High Speed mode (HS) with the bit rate up to 3.4 Mbit/s.
An I²C bus node can operate either as a master or a slave:
 Master node – issues the clock and addresses slaves
 Slave node – receives the clock line and address.
The FT4222H can operate as a master or slave, and is capable of being set to the speed modes defined in
the I²C bus specification. Besides the speed mode defined in the I²C standard specification, the I²C
controller of the FT4222H can support flexible SCL frequencies defined by the following function
𝑺𝑪𝑳
𝑭𝒓𝒆𝒒
=
𝐎𝐩𝐞𝐫𝐚𝐭𝐢𝐧𝐠 𝐂𝐥𝐨𝐜𝐤 𝐅𝐫𝐞𝐪𝐮𝐞𝐧𝐜𝐲
𝐌∗(𝐍+𝟏)
𝑴 = 𝟔 𝒐𝒓 𝟖; 𝑵 = 𝟏, 𝟐, 𝟑, … … , 𝟏𝟐𝟕
When the target frequency is below 100 KHz, M will be equal to 8; otherwise, M will be equal to 6. For
example, to generate a 2.5MHz frequency on SCL, M will be selected as 6. Then with an operating clock
frequency equal to 60MHz the user can set N as 3. The SCL frequency for I²C master mode can be set via
the FT4222_I2CMaster_Init command defined in the support library, LibFT4222. Refer to the User Guide
For LibFT4222 for further details.
5.3.1 I²C Pin Definition
The I²C function in the FT4222H is a fully configurable I²C master/slave device. When the chip
configuration is set as CNFMODE0 or CNFMODE3 and the USB-to-I²C bridge function is enabled via the
FT4222_I2CMaster_Init API which is defined in the support library LibFT4222. The pins of the FT4222H
will be mapped accordingly. The I²C pins are
 Clock – SCL (pin-13), as clock output with open-drain design when I²C bus is set as master.
as clock input when I²C bus is set as slave.
 Data – SDA (pin-14), command/address/data transfer between master and slave with open-
drain design
5.3.2 I²C Bus Protocol
There are four potential modes of operation for a given bus device, although most devices only use a
single role (Master or Slave) and its two modes (Transmit and Receive):
 Master transmit – sending data to a slave
 Master receive – receiving data from a slave
 Slave transmit – sending data to a master
 Slave receive – receiving data from the master
The following figure shows the basic I²C bus protocol
Figure 5.6 I²C Bus Protocol
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