FT4222HQ-C-R Datasheet, PDF (17/49 Pages) Future Technology Devices International Ltd. – USB2.0 to QuadSPI/I2C Bridge IC

FT4222H USB2.0 TO QUADSPI/I2C BRIDGE IC
1.3
Document No.: FT_001011 Clearance No.: FTDI#405
5.2.3 SCK Format
Software can select any of four combinations of serial clock (SCK) phase and polarity. The clock polarity
is specified by the CPOL control bit, which selects an active high or active low clock and has no significant
effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally
different transfer formats. The clock phase and polarity should be identical for the master SPI device and
the communicating slave device. In some cases, the phase and polarity are changed between transfers to
allow a master device to communicate with peripheral slaves having different requirements. The flexibility
of the SPI system on the QuadSPI allows direct interface to almost any existing synchronous serial
peripheral. Users can also use the FT4222_SPIMaster_Init API which is defined in the support library
LibFT4222 to select the operating phase and polarity of SCK.
5.2.3.1 CPHA=0 Transfer Format
Figure5.3 shows a timing diagram of an SPI transfer where CPHA is equal to 0. Two waveforms are
shown for SCK: one for CPOL equal to 0 and another for CPOL equal to 1. The diagram may be
interpreted as a master or slave timing diagram since the SCK, master in/slave out (MISO), and master
out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
Figure 5.3 SCK Transfer Format when CPHA=0
5.2.3.2 CPHA=1 Transfer Format
Figure 5.4 is a timing diagram of an SPI transfer where CPHA equal to 1. Two waveforms are shown for
SCK: one for CPOL equal to 0 and another for CPOL equal to 1. The diagram may be interpreted as a
master or slave timing diagram since the SCK, MISO, and MOSI pins are directly connected between the
master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output
from the master. The SS line is the slave select input to the slave.
Figure 5.4 SCK Transfer Format when CPHA=1
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