FT600Q Datasheet, PDF (11/32 Pages) Future Technology Devices International Ltd. – Future Technology Devices International Ltd.

FT600Q-FT601Q IC DatasheetDatasheet
Version 1.02
D oc ument N o.: FT _001118
C learance N o.: FT D I#424
Data written into the FIFO using the WR pin is stored in the FIFO TX (transmit) Buffer. The USB host
controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data
IN endpoint. (TX relative to the USB interface).
When the FT600 or FT601 is configured as the 245 Synchronous FIFO bus or 1 channel in the multi-
Channel FIFO bus mode, the FIFO buffer is configured as 4 KB * 2 (double buffered) each on the RX and
TX channels.
When the FT600 or FT601 is configured as 2 channels in the multi-Channel FIFO bus mode, the FIFO
buffer is configured as 2 KB * 2 (double buffered) each on RX and TX channel.
When the FT600 or FT601 is configured as 4 channels in the multi-Channel FIFO bus mode, the FIFO
buffer is configured as 1 KB * 2 (double buffered) each on RX and TX channel.
Internal LDO Regulator.
The LDO regulator generates the +1.0V power supply for driving the internal core of the device. Not to be
used for external devices.
Reset Generator.
The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at
power up. The RESET_N input pin allows an external device to reset the FT60x. Active low.
Remote Wake Up Function.
If USB is in suspend mode, and remote wake up has been enabled, driving the WAKEUP_N pin to low will
cause the FT60x device to request a resume from suspend on the USB bus. Normally this can be used to
w ake up the host PC from suspend.
BCD(Battery Charge Detection) Function.
Supports Battery Charging spec revision 1.2, it is optional for mapping the GPIO pin to indicate the detect
results. Refer to GPIO for the pin configuration in BCD mode.
GPIO (General purpose input and output) pins
GPOI[1:0] are multifunctional pins. The functions are configured by the chip configuration data. The
default chip configuration sets the GPIO pins as FIFO mode configuration input. At the power up, FT600
or FT601 sets the chip to 245 synchronous FIFO mode or multi-channel FIFO modes depending on the
GPIO[1:0] input, details in the table below:
GPIO1
0
0
1
1
GPIO0
0
1
0
1
C hip mode
1 channel, 245 Synchronous FIFO mode
1 channel, Multi-Channel FIFO mode
2 channel, Multi-Channel FIFO mode
4 channel, Multi-Channel FIFO mode
To enable the GPIO function, the chip configuration must be updated to set the GPIO function.
To enable the BCD mode, the chip configuration must be updated to set the BCD mode.
When the FT600 or FT601 is configured to support BCD, the GPIO pins are set to output, output changes
according to BCD detection result.
GPIO1 GPIO0 C hip mode
0
0
No USB connection or BCD detection on going.
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