IMX51A Datasheet, PDF (94/160 Pages) Freescale Semiconductor, Inc – i.MX51A Automotive and Infotainment Applications Processors

Electrical Characteristics
9_{Display control up for read}
Tdicur
=
12-- _{⎝⎛TDI_CLK × ceil}
---2-----^×-----D----I--S----P----_---U-----P----_---#----
DI_CLK_PERIOD
⎞
⎠
DISP_UP is predefined in REGISTER
10_{Display control down for read}
Tdicdrw
=
1--
2
⎝⎛^TDI_CLK
×
ce
il
-2----^×------D----I--S----P----_---D-----O----W------N----_----#-
DI_CLK_PERIOD
⎞
⎠
DISP_DOWN is predefined in REGISTER
11_{Display control up for write}
Tdicuw
=
1--
2
⎝⎛ ^TDI_CLK
×
ce
il
---2-----^×-----D-----I-S----P----_----U----P----_---#----
DI_CLK_PERIOD
⎞
⎠
DISP_UP is predefined in REGISTER
12_{This parameter is a requirement to the display connected to the IPU}
13_{Data read point}
Tdrp
=
TDI_CLK × ceil
D-----I--S----P----#---_---R----E-----A----D----_---E----N---
DI_CLK_PERIOD
Note: DISP#_READ_EN—operand of DC’s MICROCDE READ command to sample incoming data
14_{Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a}
chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
3.7.8.8 Standard Serial Interfaces
The IPU supports the following types of asynchronous serial interfaces:
1. 3-wire (with bidirectional data line).
2. 4-wire (with separate data input and output lines).
3. 5-wire type 1 (with sampling RS by the serial clock).
4. 5-wire type 2 (with sampling RS by the chip select signal).
The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire
interfaces.
Figure 61 depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to
active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal.
For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and
output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide
joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D
signal provided by the IPU.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1
94
Freescale Semiconductor
Preliminary—Subject to Change Without Notice