IMX51A Datasheet, PDF (51/160 Pages) Freescale Semiconductor, Inc – i.MX51A Automotive and Infotainment Applications Processors

3.6.8 SDRAM Controller Timing Parameters
3.6.8.1 Mobile DDR SDRAM Timing Parameters
Electrical Characteristics
SDCLK
SDCLK
CS
DD4
DD1
DD2
DD3
RAS
DD5
DD4
CAS
DD4
DD5
WE
DD6
ADDR
ROW/BA
DD7
COL/BA
DD5
DD5
Figure 29. Mobile DDR SDRAM Basic Timing Parameters
Table 42. Mobile DDR SDRAM Timing Parameter Table
200 MHz
166 MHz
133 MHz
ID
Parameter
Symbol
Unit
Min Max Min Max Min Max
DD1 SDRAM clock high-level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 tCK
DD2 SDRAM clock low-level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 tCK
DD3 SDRAM clock cycle time
tCK
5
—
6
—
7.5
—
ns
DD4 CS, RAS, CAS, CKE, WE setup time
tIS¹
0.9
—
1.1
—
1.3
—
ns
DD5 CS, RAS, CAS, CKE, WE hold time
tIH¹
0.9
—
1.1
—
1.3
—
ns
DD6 Address output setup time
tIS¹
0.9
—
1.1
—
1.3
—
ns
DD7 Address output hold time
tIH¹
0.9
—
1.1
—
1.3
—
ns
1 _{This parameter is affected by pad timing. if the slew rate is < 1 V/ns, 0.2 ns should be added to the value. For cmos65 pads}
this is true for medium and low drive strengths.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1
Freescale Semiconductor
51
Preliminary—Subject to Change Without Notice